DS90UR908Q Datasheet, PDF (8/30 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
FPD-Link II
SSC[2:0] = 000
5 MHz
t_DDLT
Lock Time
Figure 6
SSC[2:0] = 111
SSC[2:0] = 000
5 MHz
65 MHz
SSC[2:0] = 111
65 MHz
t_IJIT
Input Jitter Tolerance
Figure 9
EQ = Off
SSC[2:0] = 000
TxCLKOUT± = 65 MHz
Input Jitter Frequency <
2 MHz
Input Jitter Frequency >
6 MHz
FPD-Link Output
t_TLHT
t_THLT
t_DCCJ
Low to High Transition Time
High to Low Transition Time
Cycle-to-Cycle Output Jitter
(Note 7, Note 9, Note 10)
R_L = 100Ω
5 MHz
65 MHz
TxCLKOUT±,
TxOUT[3:0]±
TxCLKOUT±
t_TTP1
Transmitter Pulse Position for
bit 1
t_TTP0
Transmitter Pulse Position for
bit 0
t_TPP6
Transmitter Pulse Position for
bit 6
t_TTP5
Transmitter Pulse Position for 5 - 65 MHz
bit 5
Figure 8
TxOUT[3:0]±
t_TTP4
Transmitter Pulse Position for
bit 4
t_TTP3
Transmitter Pulse Position for
bit 3
t_TTP2
Transmitter Pulse Position for
bit 2
Δt_TTP
Offset Transmitter Pulse
Position (bit 6— bit 0)
65 MHzFigure 8
t_DD
t_TPDD
Delay-Latency
Power Down Delay
active to OFF
Figure 3
65 MHz
Figure 4
t_TXZR
Enable Delay
OFF to active
65 MHz
Figure 5
LVCMOS Outputs
t_CLH
t_CHL
t_PASS
Low to High Transition Time
High to Low Transition Time
BIST PASS Valid Time,
BISTEN = 1, Figure 10
C_L = 8 pF
Figure 2
5 MHz
65 MHz
LOCK, PASS
PASS
SSCG Mode
f_DEV
Spread Spectrum
Clocking Deviation
Frequency
(Note 10)
TxCLKOUT = 5 to 65
MHz,
±0.5
SSC[2:0] = ON
f_MOD
Spread Spectrum
Clocking Modulation
Frequency
(Note 10)
TxCLKOUT = 5 to 65
MHz,
8
SSC[2:0] = ON
Typ
7
14
6
8
>0.9
> 0.5
0.3
0.3
900
75
1
2
3
4
5
6
7
< +0.1
10*T
7
40
5
5
570
50
Max
0.6
0.6
2100
125
12
55
15
15
580
65
±2
100
Units
ms
ms
ms
ms
UI
UI
ns
ns
ps
ps
UI
UI
UI
UI
UI
UI
UI
UI
T
ns
ns
ns
ns
ns
ns
%
kHz
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