DS90UR908Q Datasheet, PDF(25/30 Page) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

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DS90UR908Q Datasheet, PDF (25/30 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

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POWER UP REQUIREMENTS AND PDB PIN

The VDD (VDDn), VDDTX and VDDIO supply ramps should be

faster than 1.5 ms with a monotonic rise. Supplies may power

up in any order, however device operation should be initiated

only after all supplies are in their valid operating ranges. The

optional serial bus address selection is done upon power up

also. Thus, if using this optional feature, the PDB signal must

be delayed to allow time for the ID setting to occur. The delay

maybe done by simply holding the PDB pin at a Low, or with

an external RC delay based off the VDDIO rail which would then

need to lag the others in time. If the PDB pin is pulled to

VDDIO, it is recommended to use a 10 kÎ© pull-up and a 10 uF

cap to GND to delay the PDB input signal.

TRANSMISSION MEDIA

The FPD-Link II chipset is intended to be used in a point-to-

point configuration, through a PCB trace, or through twisted

pair cable. The serializer and deserializer provide internal ter-

minations providing a clean signaling environment. The inter-

connect for LVDS should present a differential impedance of

100 Ohms. Use cables and connectors that have matched

differential impedance to minimize impedance discontinuities.

Shielded or un-shielded cables may be used depending upon

the noise environment and application requirements.

LIVE LINK INSERTION

The serializer and deserializer devices support live pluggable

applications. The automatic receiver lock to random data

âplug & goâ hot insertion capability allows the DS90UR908Q

to attain lock to the active data stream during a live insertion

event.

ALTERNATE COLOR / DATA MAPPING

Color Mapped data Pin names are provided to specify a rec-

ommended mapping for 24-bit and 18-bit Applications. When

connecting to earlier generations of FPD-Link II serializer de-

vices, a color mapping review is recommended to ensure the

correct connectivity is obtained. Table 9 provides examples

for interfacing between DS90UR908Q and different deserial-

izers.

TABLE 9. Alternate Color / Data Mapping

FPD-Link

TxOUT3

TxOUT2

TxOUT1

TxOUT0

Bit Number

Bit 26

Bit 25

Bit 24

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

RGB (LSB

Example)

DS90UR908Q

Settings

MAPSEL = 0

DS90UR905Q DS90UR241 DS99R421 DS90C241

N/ADIN12

CONFIG [1:0] = 00

N/A

DIN20

RxIN2

DIN19

DIN18

DIN17

DIN16

DIN15

DIN14

DIN13

RxIN1

DIN12

DIN11

DIN10

DIN9

DIN8

DIN7

DIN6

RxIN0

DIN5

DIN4

DIN3

DIN2

DIN1

DIN0

DIN23

OS2

DIN22

OS1

DIN21

OS0

CONFIG [1:0] = 10