DS90UR908Q Datasheet, PDF (19/30 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

Built In Self Test (BIST) — Optional
An optional At-Speed Built In Self Test (BIST) feature sup-
ports the testing of the high-speed serial link. This is useful in
the prototype stage, equipment production, in-system test
and also for system diagnostics. In the BIST mode only an
input clock is required along with control to the Ser and Des
BISTEN input pins. The Ser outputs a test pattern (PRBS7)
and drives the link at speed. The Des detects the PRBS7 pat-
tern and monitors it for errors. The PASS output pin toggles
to flag any payloads that are received with 1 to 24 bit errors.
The BISTM pin selects the operational mode of the PASS pin.
If BISTM = L, the PASS pins reports the final result only. If
BISTM = H, the PASS pins counts payload errors and also
results the result. The result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on
PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of
the test is controlled by the pulse width applied to the Des
BISTEN pin.
Sample BIST Sequence
SeeFigure 18 for the BIST mode flow diagram.
Step 1: Place the DS90UR907Q or DS90UR905Q in BIST
Mode by setting BISTEN = H. The BIST Mode is enabled via
the BISTEN pin. An RxCLKIN or PCLK is required for all the
Ser options. When the DS90UR908Q detects the BIST mode
pattern and command (DCA and DCB code) the RGB and
control signal outputs are shut off.
Step 2: Place the DS90UR908Q in BIST mode by setting the
BISTEN = H. The Device is now in the BIST mode and checks
the incoming serial payloads for errors. If an error in the pay-
load (1 to 24) is detected, the PASS pin will switch low for one
half of the clock period. During the BIST test, the PASS output
can be monitored and counted to determine the payload error
rate.
Step 3: To Stop the BIST mode, the DS90UR908Q BISTEN
pin is set Low. It stops checking the data and the final test
result is held on the PASS pin. If the test ran error free, the
PASS output will be High. If there was one or more errors
detected, the PASS output will be Low. The PASS output
state is held until a new BIST is run, the device is RESET, or
Powered Down. The BIST duration is user controlled by the
duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer
BISTEN input is set Low. The Link returns to normal opera-
tion.
Figure 19 shows the waveform diagram of a typical BIST test
for two cases. Case 1 is error free, and Case 2 shows one
with multiple errors. In most cases it is difficult to generate
errors due to the robustness of the link (differential data trans-
mission etc.), thus they may be introduced by greatly extend-
ing the cable length, faulting the interconnect, reducing signal
condition enhancements (De-Emphasis, VODSEL, or Rx
Equalization).
30105143
FIGURE 18. BIST Mode Flow Diagram
19
www.national.com