DS90UR908Q Datasheet, PDF (4/30 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

Pin Name
Pin #
I/O, Type
Optional Serial Bus Control Interface
SCL
5
I, LVCMOS
SDA
ID[x]
4
I/O,
LVCMOS
Open Drain
12
I, Analog
Power and Ground
VDDL
6, 31
VDDA
38, 43
VDDP
8
VDDSC
46, 47
VDDTX
13
V_DDIO
GND
25
9, 14, 26,
32, 39, 44,
45, 48
DAP
DAP
Power
Power
Power
Power
Power
Power
Ground
Ground
Description
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor to V_DDIO.
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 7.
Logic Power, 1.8 V ±5%
Analog Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
SSC Generator Power, 1.8 V ±5%
FPD-Link Power, 3.3 V ±10%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connect to the ground plane (GND) with at least 9 vias.
NOTE: 1 = HIGH, 0 = LOW
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