COP8782C Datasheet, PDF (8/28 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller

Functional Description (Continued)
FIGURE 6 Interrupt Block Diagram
TL DD 11299 – 9
DETECTION OF ILLEGAL CONDITIONS
The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding
errors noise and ‘‘brown out’’ voltage drop situations Spe-
cifically it detects cases of executing out of undefined EP-
ROM area and unbalanced stack situations
Reading an undefined EPROM location returns 00 (hexade-
cimal) as its contents The opcode for a software interrupt is
also ‘‘00’’ Thus a program accessing undefined EPROM
will cause a software interrupt
Reading an undefined RAM location returns an FF (hexade-
cimal) The subroutine stack on the device grows down for
each subroutine call By initializing the stack pointer to the
top of RAM the first unbalanced return instruction will cause
the stack pointer to address undefined RAM As a result the
program will attempt to execute from FFFF (hexadecimal)
which is an undefined EPROM location and will trigger a
software interrupt
MICROWIRE PLUS
MICROWIRE PLUS is a serial synchronous bidirectional
communications interface The MICROWIRE PLUS capabil-
ity enables the device to interface with any of National
Semiconductor’s MICROWIRE peripherals (i e A D con-
verters display drivers EEPROMS etc ) and with other mi-
crocontrollers which support the MICROWIRE PLUS inter-
face It consists of an 8-bit serial shift register (SIO) with
serial data input (SI) serial data output (SO) and serial shift
clock (SK) Figure 7 shows the block diagram of the MICRO-
WIRE PLUS interface
TL DD 11299–10
FIGURE 7 MICROWIRE PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source Operating the MICROWIRE
PLUS interface with the internal clock source is called the
Master mode of operation Operating the MICROWIRE
PLUS interface with an external shift clock is called the
Slave mode of operation
The CNTRL register is used to configure and control the
MICROWIRE PLUS mode To use the MICROWIRE PLUS
the MSEL bit in the CNTRL register is set to one The SK
clock rate is selected by the two bits SL0 and SL1 in the
CNTRL register Table IV details the different clock rates
that may be selected
TABLE IV
SL1
SL0
SK Cycle Time
0
0
2t_c
0
1
4t_c
1
x
8t_c
where
t_c is the instruction cycle time
MICROWIRE PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MI-
CROWIRE PLUS arrangement to start shifting the data It
gets reset when eight data bits have been shifted The user
may reset the BUSY bit by software to allow less than 8 bits
to shift The device may enter the MICROWIRE PLUS
mode either as a Master or as a Slave Figure 8 shows how
two device microcontrollers and several peripherals may be
interconnected using the MICROWIRE PLUS arrangement
Master MICROWIRE PLUS Operation
In the MICROWIRE PLUS Master mode of operation the
shift clock (SK) is generated internally by the device The
MICROWIRE PLUS Master always initiates all data ex-
changes (Figure 8) The MSEL bit in the CNTRL register
must be set to enable the SO and SK functions on the G
Port The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration regis-
ter Table V summarizes the bit settings required for Master
mode of operation
SLAVE MICROWIRE PLUS OPERATION
In the MICROWIRE PLUS Slave mode of operation the SK
clock is generated by an external source Setting the MSEL
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