COP8782C Datasheet, PDF (3/28 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller

COP8780C COP8781C COP8782C
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V_CC)
Programming Voltage V_PP (RESET pin)
and ME (pin G6)
7V
13 4V
Voltage at any Pin
b0 3V to V_CC a 0 3V
Total Current into V_CC Pin (Source)
Total Current out of GND Pin (Sink)
50 mA
60 mA
Storage Temperature Range
b65 C to a150 C
Note Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics COP87XXC b40 C ^s T_A ^s a85 C unless otherwise specified
Parameter
Condition
Min
Typ
Max
Operating Voltage
Power Supply Ripple (Note 1)
Supply Current
CKI e 10 MHz (Note 2)
HALT Current (Note 3)
Input Levels
RESET CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
45
Peak to Peak
V_CC e 6V t_c e 1 ms
V_CC e 6V CKI e 0 MHz
60
0 1 V_CC
21
10
V_CC e 6 0V
V_CC e 6 0V V_IN e 0V
(Note 6)
0 9 V_CC
0 7 V_CC
b2
b40
0 05 V_CC
0 1 V_CC
0 2 V_CC
a2
b250
V_CC e 4 5V V_OH e 3 8V
V_CC e 4 5V V_OL e 1 0V
V_CC e 4 5V V_OH e 3 2V
V_CC e 4 5V V_OH e 3 8V
V_CC e 4 5V V_OL e 0 4V
b0 4
10
b10
b0 4
16
b2 0
b110
a2 0
Allowable Sink Source
Current per Pin
D Outputs (Sink)
15
All Others
3
Maximum Input Current (Notes 4 6)
without Latchup (Room Temp)
Room Temp
g200
RAM Retention Voltage Vr
(Note 5)
20
Input Capacitance
(Note 6)
7
Load Capacitance on D2
(Note 6)
1000
Units
V
V
mA
mA
V
V
V
V
mA
mA
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
pF
pF
Note 1 Rate of voltage change must be less than 0 5V ms
Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open
Note 3 The HALT mode will stop CKI from oscillating in the RC and the crystal configurations Halt test conditions All Inputs tied to V_CC L C and G port I O’s
configured as outputs and programmed low D outputs programmed low the window for UV erasable packages is completely covered with an opaque cover to
prevent light from falling onto the die during HALT mode test Parameter refers to HALT mode entered via setting bit 7 of the G Port data register
Note 4 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than V_CC and the pins will
have sink current to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC) The effective
resistance to V_CC is 750X (typ) These two pins will not latch up The voltage at the pins must be limited to less than 14V
Note 5 To maintain RAM integrity the voltage must not be dropped or raised instantaneously
Note 6 Parameter characterized but not tested
3
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