COP8782C Datasheet, PDF (11/28 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller

Memory Map
All RAM ports and registers (except A and PC) are mapped into data memory address space
RAM Select
64 On-Chip RAM Bytes
Selected by ECON reg
128 On-Chip RAM Bytes
Selected by ECON reg
Address
00 – 2F
30 – 7F
00 – 6F
70 – 7F
80 to BF
C0 to CF
D0 to DF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD – DF
E0 to EF
E0 – E7
E8
E9
EA
EB
EC
ED
EE
EF
F0 to FF
FC
FD
FE
Contents
48 On-Chip RAM Bytes
Unused RAM Address Space (Reads as all 1’s)
112 On-chip RAM Bytes
Unused RAM Address Space (Reads as all 1’s)
Expansion Space for On-Chip EERAM
Expansion Space for I O and Registers
On-Chip I O and Registers
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
On-Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE PLUS Shift Register
Timer Lower Byte
Timer Upper Byte
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reading unused memory locations below 7FH will return all ones Reading other unused memory locations will return undefined
data
11
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