COP8782C Datasheet, PDF (6/28 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller

Functional Description (Continued)
ers The device can be configured to have either 64 or 128
bytes of RAM depending on the value of the ‘‘RAM SIZE’’
bit in the ECON (EPROM CONFIGURATION) register The
sixteen bytes of RAM located at data memory address 0F0–
0FF are designated as ‘‘registers’’ These sixteen registers
can be decremented and tested with the DRSZ (Decrement
Register and Skip if Zero) instruction
The three pointers X B and SP are memory mapped into
this register address space at addresses 0FC 0FE and
0FD respectively The remaining registers are available for
general usage
Any bit of data memory can be directly set reset or tested
All of the I O registers and control registers (except A and
PC) are memory mapped Consequently any of the I O bits
or control register bits can be directly and individually set
reset or tested
Note RAM contents are undefined upon power-up
ECON (EPROM CONFIGURATION) REGISTER
The ECON register is used to configure the user selectable
clock security and RAM size options The register can be
programmed and read only in EPROM programming mode
Therefore the register should be programmed at the same
time as the program memory locations 0000 through 0FFF
Hex UV erasable parts are shipped with 0FF Hex in this
register while the OTP parts are shipped with 07F Hex in
this register Erasing the EPROM program memory also
erases the ECON register
The device has a security feature which when enabled pre-
vents reading of the EPROM program memory The security
bit in the ECON register determines whether security is en-
abled or disabled If the security option is enabled then any
attempt to externally read the contents of the EPROM will
result in the value E0 Hex being read from all program mem-
ory locations If the security option is disabled the contents
of the internal EPROM may be read The ECON register is
readable regardless of the state of the security bit
The format of the ECON register is as follows
TABLE I
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X SECURITY CKI 2 CKI 1 X RAM SIZE X
Bit 7 e X Don’t care
Bit 6 e X Don’t care
Bit 5 e 1 Security disabled EPROM read and write are
allowed
e 0 Security enabled EPROM read and write are
not allowed
Bits 4 3
e 1 1 External CKI option selected
e 0 1 Not allowed
e 1 0 RC oscillator option selected
e 0 0 Crystal oscillator option selected
Bit 2 e X Don’t care
Bit 1 e 1 Selects 128 byte RAM option This emulates
COP840 and COP880
e 0 Selects 64 byte RAM option This emulates
COP820
Bit 0 e X Don’t care
RESET
The RESET input when pulled low initializes the microcon-
troller Initialization will occur whenever the RESET input is
pulled low Upon initialization the Ports L G and C are
placed in the TRI-STATE mode and the Port D is set high
The PC PSW and CNTRL registers are cleared The data
and configuration registers for Ports L G and C are cleared
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes
TL DD 11299 – 7
RC t 5X Power Supply Rise Time
FIGURE 4 Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 5 shows the three clock oscillator configurations
available for the device The CKI 1 and CKI 2 bits in the
ECON register are used to select the clock option See the
ECON REGISTER section for more details
TL DD 11299 – 8
FIGURE 5 Crystal External and
R-C Connection Diagrams
A Crystal Oscillator
The device can be driven by a crystal clock The crystal
network is connected between the pins CKI and CKO
Table II shows the component values required for various
standard crystal frequencies
B External Oscillator
CKI can be driven by an external clock signal provided it
meets the specified duty cycle rise and fall times and input
levels In External oscillator mode G7 is available as a gen-
eral purpose input and or HALT restart control
http www national com
6