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DS90UR907Q_10 Datasheet, PDF (7/26 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter
Symbol
Parameter
Conditions
Min
FPD-LINK II LVDS OUTPUT
tHLT
Output Low-to-High Transition RL = 100Ω, De-emphasis = disabled,
Time
VODSEL = 0
Figure 4
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
tHLT
Output High-to-Low Transition RL = 100Ω, De-emphasis = disabled,
Time
VODSEL = 0
Figure 4
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
tXZD
Ouput Active to OFF Delay,
Figure 7
tPLD
PLL Lock Time, Figure 6
tSD
Delay - Latency, Figure 8
tDJIT
Output Total Jitter,
Figure 9
RL = 100Ω, (Note 5)
RL = 100Ω
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, RxCLKIN = 43 & 65 MHz(Note 6)
λSTXBW
Jitter Transfer
RxCLKIN = 43 MHz
Function -3 dB Bandwidth(Note
8, Note 9)
RxCLKIN = 65 MHz
δSTX
Jitter Transfer
RxCLKIN = 43 MHz
Function Peaking(Note 8, Note
9)
RxCLKIN = 65 MHz
Typ Max Units
200
ps
200
ps
200
ps
200
ps
5
15
ns
1.5
10
ms
140*T 145*T ns
0.26
UI
2.2
MHz
3
1
dB
1
Recommended Timing for the Serial Control Bus
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
fSCL
SCL Clock Frequency
Standard Mode
Fast Mode
tLOW
SCL Low Period
Standard Mode
Fast Mode
tHIGH
SCL High Period
Standard Mode
Fast Mode
tHD;STA
Hold time for a start or a
repeated start condition,
Figure 12
Standard Mode
Fast Mode
tSU:STA
Set Up time for a start or a
repeated start condition,
Figure 12
Standard Mode
Fast Mode
tHD;DAT Data Hold Time,
Figure 12
Standard Mode
Fast Mode
tSU;DAT Data Set Up Time,
Figure 12
Standard Mode
Fast Mode
tSU;STO Set Up Time for STOP
Condition, Figure 12
Standard Mode
Fast Mode
tBUF
Bus Free Time
Standard Mode
Between STOP and START,
Figure 12
Fast Mode
tr
SCL & SDA Rise Time,
Figure 12
Standard Mode
Fast Mode
tf
SCL & SDA Fall Time,
Figure 12
Standard Mode
Fast mode
Min Typ Max Units
0
100 kHz
0
400 kHz
4.7
us
1.3
us
4.0
us
0.6
us
4.0
us
0.6
us
4.7
us
0.6
us
0
3.45 us
0
0.9
us
250
ns
100
ns
4.0
us
0.6
us
4.7
us
1.3
us
1000 ns
300
ns
300
ns
300
ns
7
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