DS90UR907Q_10 Datasheet, PDF (22/26 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter

POWER UP REQUIREMENTS AND PDB PIN
The VDD (V_DDn and V_DDIO) supply ramp should be faster than
1.5 ms with a monotonic rise. If slower then 1.5 ms then a
capacitor on the PDB pin is needed to ensure PDB arrives
after all the VDD have settled to the recommended operating
voltage. When PDB pin is pulled to V_DDIO, it is recommended
to use a 10 kΩ pull-up and a 22 uF cap to GND to delay the
PDB input signal.
TRANSMISSION MEDIA
The DS90UR907Q and the companion deserializer chipset is
intended to be used in a point-to-point configuration, through
a PCB trace, or through twisted pair cable. The DS90UR907Q
provide internal terminations providing a clean signaling en-
vironment. The interconnect for LVDS should present a dif-
ferential impedance of 100 Ohms. Use cables and connectors
that have matched differential impedance to minimize
impedance discontinuities. Shielded or un-shielded cables
may be used depending upon the noise environment and ap-
plication requirements.
ALTERNATE COLOR / DATA MAPPING
Color Mapped data pin names are provided to specify a rec-
ommended mapping for 24-bit and 18-bit Applications. When
connecting to earlier generations of FPD-Link II deserializer
devices, a color mapping review is recommended to ensure
the correct connectivity is obtained. Table 6 provides exam-
ples for interfacing between DS90UR907Q and different de-
serializers.
TABLE 6. Alternate Color / Data Mapping
FPD-Link
Bit Number
RGB (LSB
Example)
RxIN3
Bit 26
B1
Bit 25
B0
Bit 24
G1
Bit 23
G0
Bit 22
R1
Bit 21
R0
RxIN2
Bit 20
DE
Bit 19
VS
Bit 18
HS
Bit 17
B7
Bit 16
B6
Bit 15
B5
Bit 14
B4
RxIN1
Bit 13
B3
Bit 12
B2
Bit 11
G7
Bit 10
G6
Bit 9
G5
Bit 8
G4
Bit 7
G3
RxIN0
Bit 6
G2
Bit 5
R7
Bit 4
R6
Bit 3
R5
Bit 2
R4
Bit 1
R3
Bit 0
R2
N/A
* These bits are not supported by
DS90UR907Q
DS90UR907Q
Settings
MAPSEL = 0
DS90UR906Q DS90UR124 DS99R124Q DS90C124
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6ROUT10
B5
B4
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
N/A
CONFIG [1:0]
= 00
N/A
ROUT20
TxOUT2
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
ROUT13
TxOUT1
ROUT12
ROUT11
ROUT10
ROUT9
ROUT8
ROUT7
ROUT6
TxOUT0
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
ROUT0
ROUT23*
OS2*
ROUT22*
OS1*
ROUT21*
OS0*
CONFIG [1:0] = 10
ROUT20
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
ROUT13
ROUT12
ROUT11
ROUT10
ROUT9
ROUT8
ROUT7
ROUT6
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
ROUT0
ROUT23*
ROUT22*
ROUT21*
CONFIG [1:0]
= 11
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