DS90UR907Q_10 Datasheet, PDF (21/26 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter

Applications Information
DISPLAY APPLICATION
The DS90UR907Q and DS90UR908Q chipset is intended for
interface between a host (graphics processor) and a Display.
It supports an 24-bit color depth (RGB888) and up to 1024 X
768 display formats. In a RGB888 application, 24 color bits
(R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control
bits (VS, HS and DE) are supported across the serial link with
PCLK rates from 5 to 65 MHz. The chipset may also be used
in 18-bit color applications. In this application three to six gen-
eral purpose signals may also be sent from host to display.
TYPICAL APPLICATION CONNECTION
Figure 25 shows a typical application of the DS90UR907Q for
a 65 MHz 24-bit Color Display Application. The LVDS inputs
of the FPD-Link interface require external 100Ω terminations.
The LVDS outputs of FPD-Link II require 100 nF AC coupling
capacitors to the line. The line driver includes internal termi-
nation. Bypass capacitors are placed near the power supply
pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF ca-
pacitor should be used for local device bypassing. System
GPO (General Purpose Output) signals control the PDB and
BISTEN pins. The application assumes the companion de-
serializer (DS90UR908Q) therefore the configuration pins are
also both tied Low. In this example the cable is long, therefore
the VODSEL pin is tied High and a De-Emphasis value is se-
lected by the resistor R1. The interface to the host is with 1.8
V LVCMOS levels, thus the VDDIO pin is connected also to
the 1.8V rail. The Optional Serial Bus Control is not used in
this example, thus the SCL, SDA and ID[x] pins are left open.
A delay capacitor and resistor is placed on the PDB signal to
delay the enabling of the device until power is stable. Bypass
capacitors are placed near the power supply pins. Ferrite
beads are placed on the power lines for effective noise sup-
pression.
FIGURE 25. Typical Connection Diagram
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