PC87365 Datasheet, PDF (67/215 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring

2.0 Device Architecture and Configuration (Continued)
2.15.3 KBC Configuration Register
This register is reset by hardware to 40h.
Location: Index F0h
Type:
R/W
Bit
7
6
Name
KBC Clock Source
Reset
0
1
Required
5
4
Reserved
0
0
3
Swap
0
2
1
Reserved
0
0
0
0
TRI-STATE
Control
0
Bit
Description
7-6 KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled).
Bits
7 6 Source
0 0 8 MHz
0 1 12 MHz (default)
1 0 16 MHz
1 1 Reserved
5-4 Reserved.
3 Swap. This bit swaps between the KBD and Mouse interface pins.
0: KBCLK and KBDAT are KBD interface; MCLK and MDAT are Mouse interface (default)
1: KBCLK and KBDAT are Mouse interface, MCLK and MDAT are KBD interface
2-1 Reserved.
0 TRI-STATE Control. If KBD is inactive (disabled) when this bit is set, the KBD pins (KBCLK and KBDAT) are in TRI-
STATE. If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MDAT) are in TRI-STATE.
0: Disabled (default)
1: Enabled
Usage Hints:
To change the clock frequency of the KBC:
1. Disable the KBC logical devices.
2. Change the frequency setting.
3. Enable the KBC logical devices.
4. Before swapping between the KBD and Mouse interface pins, disable the KBC logical devices and both pin sets. After
swapping, the software should issue a synchronization command to the KBD and mouse through the KBC to regain syn-
chronization with these devices.
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