PC87365 Datasheet, PDF (60/215 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring

2.0 Device Architecture and Configuration (Continued)
2.11.2 Logical Device 1 (PP) Configuration
Table 21 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Sec-
tions 2.2.3 and 2.2.4 for descriptions of the others.
Table 21. Parallel Port Configuration Registers
Index
Configuration Register or Action
Type
30h Activate. See also bit 0 of the SIOCF1 register.
R/W
60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for R/W
A10) should be 0b.
61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP R/W
Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.
70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35).
R/W
71h Interrupt Type
R/W
Bits 7-2 are read only.
Bit 1 is a read/write bit.
Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation
mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge
interrupt) in all other modes.
74h DMA Channel Select.
R/W
75h Report no second DMA assignment.
RO
F0h Parallel Port Configuration register.
R/W
Reset
00h
02h
78h
07h
02h
04h
04h
F2h
www.national.com
60