PC87365 Datasheet, PDF (155/215 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring

9.0 Voltage Level Monitor (VLM) (Continued)
Analog
Power ^R1 ^{10 Ω}
AD0
AD0
V_IN
AD6
AD6
V_REF
V_REF
C₁
0.47
µF
+
C₂
22
µF
C₃
0.1
µF
V_REF
AV_DD
AV_SS
Power
Supply
3.3 V
V_SB
GND
+ C₅
22
C₄ 0.1
µF
µF
Analog Ground Layer
Digital Ground Layer
Figure 29. Analog Power Supply
9.3.2 Reference Voltage
Analog input voltage is measured relative to (2.45±0.05)*V_REF. V_REF may be either internal or external. When an internal
V_REF is used, a capacitor should be connected between the V_REF pin and AV_SS. The V_REF default setting is for external.
This default prevents contention between the internal and external V_REF.
Note that the V_REF setting is common to both the VLM and the TMS modules. If either of these modules is configured to use
internal reference voltage, the internal reference voltage is used by both modules.
9.4 REGISTER BANK OVERVIEW
The VLM uses register banks to enable host access to its registers. The VLM has 10 common registers in addition to four
registers that are located in each of the 10 banks. The common registers include configuration and status information com-
mon to all the channels. Each of the banks is associated with one channel and holds its readout, configuration and status
information. All registers use the same 16-byte address space to indicate offsets 00h through 0Fh. The active bank must be
selected by the software.
The VLM Bank Selection (VLMBS) register, which is common to all banks, selects the active banks (see Figure 30). The
default bank selection after system reset is 0.
Offset 00h
.
.
.
Offset 08h
} Common
Registers
for
All Banks
VLMBS (09h)
Offset 0Ah
Offset 0Bh
Offset 0Eh
Offset 0Fh
BANK 10
BANK 1
BANK 0
Figure 30. Register Bank Architecture
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