PC87365 Datasheet, PDF (111/215 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring

3.0 System Wake-Up Control (SWC) (Continued)
X = port number
n = pin number, 0 to 7
SBGPIOX Base Address
8 SBGPIO Pin Configuration
Registers
Bit n
SBGPDOX _Runtime
SBGPDIX ^Registers
SBGPIO Pin
Configuration Register
SBGPIOXn CNFG
SBGPIOXn
Pin Logic
SBGPIO Port X
Pin n
SBGPIO Pin
Select Register
Port and Pin
Select
Event
Pending
Indicator
x8
x8
x8
To Wake-Up
Logic
Figure 11. SBGPIO Port Architecture
Basic Functionality
The basic functionality of each SBGPIO pin is based on four configuration bits and a bit slice of runtime registers SBGPDO
and SBGPDI. The configuration and operation of a single pin (pin n in port X) is shown in Figure 12.
Read Only
Data In
Read/Write
Data Out
Push-Pull=1
Static
Pull-Up
Pin
Internal
Bus
Pull-Up
Enable
Lock
Pull-Up
Control
Output
Type
Output
Enable
Bit 3
Bit 2
Bit 1
Bit 0
SBGPIO Pin Configuration Register
Figure 12. SBGPIO Basic Functionality
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