DS90CR486 Datasheet, PDF (6/15 Pages) National Semiconductor (TI) – 133MHz 48-Bit Channel Lick Deserializer (6.384 Gbps)

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
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Tppos — Transmitter output pulse position (min and max)
RSKMD = ISI (Inter-symbol interference) + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 8: Refer to transmitter datasheet for Cycle-to-cycle LVDS Output jitter specification.
Note 9: ISI is dependent on interconnect length; may be zero. Pre-emphasis in the transimitter is used to reduce the ISI. Refer to transmitter datasheet for more
information.
FIGURE 7. Receiver Skew Margin with DESKEW (RSKMD)
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