DS90CR486 Datasheet, PDF (12/15 Pages) National Semiconductor (TI) – 133MHz 48-Bit Channel Lick Deserializer (6.384 Gbps)

Applications Information (Continued)
HOW TO CONFIGURE FOR BACKPLANE
APPLICATIONS
In a backplane application with differential line impedance of
100Ω the differential line pair-to-pair skew can controlled by
trace layout. The transmitter-DS90CR485 “DS_OPT” pin
may be set high. In a backplane application with short PCB
distance traces, pre-emphasis from the transmitter is typi-
cally not required. The “PRE” pin should be left open (do not
tie to ground). A resistor pad provision for a pull up resistor to
Vcc can be implemented in case pre-emphasis is needed to
counteract heavy capacitive loading effects.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins.
Different pins supply different portions of the circuit, there-
fore capacitors should be nearby all power supply pins ex-
cept as noted in the pin description table. Use high fre-
quency ceramic (surface mount recommended) 0.1µF
capacitors close to each supply pin. If space allows, a
0.01µF capacitor should be used in parallel, with the small-
est value closest to the device pin. Additional scattered
capacitors over the printed circuit board will improve decou-
pling. Multiple (large) via should be used to connect the
decoupling capacitors to the power plane. A 4.7 to 10µF bulk
cap is recommended near the PLLVCC pins and also the
LVDSVCC pins. Connections between the caps and the pin
should use wide traces.
RECEIVER OUTPUT DRIVE STRENGTH
The DS90CR486 output specifies a 8pF load, V_OH and V_OL
are tested at ± 2mA, which is intended for only 1 or maybe
2 loads. The DS90CR486 reciever’s output driving capability
has improved over prior generation of Channel Link devices.
Additional buffering at the reciver output is not necessary. If
high fan-out is required or long transmission line driving
capability, buffering the receiver output is recommended.
Receiver outputs do not support / provide a TRI-STATE
function.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
— S = space between the pair
— 2S = space between pairs
— 3S = space to TTL signal
• Minimize the number of VIA
• Use differential connectors when operating above
500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Minimize skew between pairs
• Terminate as close to the RXinputs as possible
For more information:
Channel Link Applications Notes currently available:
• AN-1041 Introduction to Channel Link
• AN-1108 PCB and Interconnect Guidelines
• AN-905 Differential Impedance
• National’s LVDS Owner’s Manual
www.national.com
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