DS90CR486 Datasheet, PDF (11/15 Pages) National Semiconductor (TI) – 133MHz 48-Bit Channel Lick Deserializer (6.384 Gbps)

Applications Information
DC BALANCE
In addition to data information an additional bit is transmitted
on every LVDS data signal line during each cycle as shown
in Figure 9. This bit is the DC balance bit (DCB). The
purpose of the DC Balance bit is to minimize the short- and
long-term DC bias on the signal lines. This is achieved by
selectively sending the data either unmodified or inverted.
The value of the DC balance bit is calculated from the
running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall
be calculated by subtracting the number of bits of value 0
from the number of bits value 1 in the current word. Initially,
the running word disparity may be any value between +7 and
−6. The running word disparity shall be calculated as a
continuous sum of all the modified data disparity values,
where the unmodified data disparity value is the calculated
data disparity minus 1 if the data is sent unmodified and 1
plus the inverse of the calculated data disparity if the data is
sent inverted. The value of the running word disparity shall
saturate at +7 and −6.
The value of the DC balance bit (DCB) shall be 0 when the
data is sent unmodified and 1 when the data is sent inverted.
To determine whether to send data unmodified or inverted,
the running word disparity and the current data disparity are
used. If the running word disparity is positive and the current
data disparity is positive, the data shall be sent inverted. If
the running word disparity is positive and the current data
disparity is zero or negative, the data shall be sent unmodi-
fied. If the running word disparity is negative and the current
data disparity is positive, the data shall be sent unmodified.
If the running word disparity is negative and the current data
disparity is zero or negative, the data shall be sent inverted.
If the running word disparity is zero, the data shall be sent
inverted.
DC Balance mode is set when the BAL pin on the transmitter
and receiver are tied HIGH - see pin descriptions.
DESKEW
The "DESKEW” function on this receiver will deskew or
compensate fixed interconnect skew between data signals,
with respect to the rising edge of the LVDS clock, on each of
the independent differential pairs (pair-to-pair skew). The
deskew initialization or calibration is done automatically
when the device is powered up. The control pin CON1 must
set High and the Deskew pin must set to High on the
DS90CR486. However, the Deskew calibration can also be
performed after the device is powered up. De-asserting with
a pulse of duration greater than one clock cycle to the
Deskew pin to restart the calibration of deskew. The calibra-
tion takes 4096 clock cycles to complete after the TX and RX
PLLs lock (20ms). No RxIN data is sampled during this
period. The data outputs during this period will be Low. For
normal operation, deskew pin must set to High. Setting the
deskew pin to Low or No Connect will continuously re-
calibrate the sampling strobes. Data outputs are Low during
this period.
In order for the deskew function to work properly, it must be
intialized. The DS90CR486 deskew can be initialized with
any data pattern with a transition over a period of three clock
cycles. Therefore, there are mulitiple ways to initialize the
deskew function depending on the setup configuration
(Please refer to Figure 10). For example, to initialize the
operation of deskew using DS90CR485 and DS90CR486 in
DC balance mode, the DS_OPT pin at the input of the
transmitter DS90CR485 can be set High OR Low when
powered up. The period of this input to the DS_OPT pin must
be at least 20ms (TX and RX PLLs lock time) plus 4096 clock
cycles in order for the receiver to complete the deskew
operation. For other configuration setup with DS90CR483
and DS90CR484, please refer to the flow chart on Figure 10.
The DS_OPT pin at the input of the transmitter
(DS90CR485) can be used to initiate the deskew calibration
pattern. Depends on the configuration, it can be set High or
applied Low when power up in order for the receiver to
complete the deskew operation. For this reason, the LVDS
clock signal with DS_OPT applied high (active data sam-
pling) shall be 1111000 or 1110000 pattern and the LVDS
data lines (TxOUT 0-7) shall be High for one clock cycle and
Low for the next clock cycle. During the deskew operation
with DS_OPT applied low, the LVDS clock signal shall be
1111100 or 1100000 pattern. The transmitter will also output
a series of 1111000 or 1110000 onto the LVDS data lines
(TxOUT 0-7) during deskew so that the receiver can auto-
matically calibrated the data sampling strobes at the receiver
inputs. Each data channel is deskewed independently and is
tuned over a specific range. Please refer to corresponding
receiver datasheet for a list of deskew ranges.
Note that the deskew initialization must be performed at
least once after the PLL has locked to the input clock fre-
quency, and it must be done at the time when the receiver is
powered up and PLL has locked. If power is lost, or if the
cable has been swithcd or disconnected, the initialization
procedure must be repeated or else the receiver may not
sample the incoming LVDS data correctly.
POWER DOWN
The receiver provides a power down feature. When de-
asserted current draw through the supply pins is minimized
and the PLLs are shut down. The receiver outputs are forced
to an active LOW state when in the power down mode. (See
Pin Description Tables). This is not a LVCMOS/LVTTL input
pin and has a high input threshold. For normal operation, this
pin must be tied to an input level of 2.5V to Vcc.
CONFIGURATIONS
The chipset is designed to be connected typically to a single
receiver load. This is known as a point-to-point configuration.
It is also possible to drive multiple receiver loads if certain
restrictions are made(i.e. low data rate). Only the final re-
ceiver at the end of the interconnect should provide termina-
tion across the pair. In this case, the driver still sees the
intended DC load of 100 Ohms. Receivers connected to the
cable between the transmitter and the final receiver must not
load down the signal. To meet this system requirement, stub
lengths from the line to the receiver inputs must be kept very
short.
CABLE TERMINATION
A termination resistor is required for proper operation to be
obtained. The termination resistor should be equal to the
differential impedance of the media being driven. This should
be in the range of 90 to 132 Ohms. 100 Ohms is a typical
value common used with standard 100 Ohm twisted pair
cables. This resistor is required for control of reflections and
also to complete the current loop. It should be placed as
close to the receiver inputs to minimize the stub length from
the resistor to the receiver input pins.
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