DS90CR486 Datasheet, PDF (10/15 Pages) National Semiconductor (TI) – 133MHz 48-Bit Channel Lick Deserializer (6.384 Gbps)

DS90CR486 Pin Description—Channel Link Receiver
Pin Name
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
PD
DESKEW
BAL
CON1
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I/O
No.
Description
I
8
Positive LVDS differential data inputs.
I
8
Negative LVDS differential data inputs.
O
48
LVCMOS/LVTTL level data outputs. In PowerDown (PD = Low) mode,
receiver outputs are forced to a Low state.
I
1
Positive LVDS differential clock input.
I
1
Negative LVDS differential clock input.
O
1
LVCMOS/LVTTL level clock output. The rising edge acts as data strobe.
I
1
Control input for PLL range select. This pin must be tied to V_CC. No
connect or tied to GND is reserved for future use.
I
1
Power Down pin. This pin must be tied to input level of 2.5V to Vcc for
normal operation. When de-asserted (low input) the receiver outputs are
Low. Please refer to the Applications Information on the back for more
information.
I
1
This pin must be tied to logic High or Vcc for normal operation of Deskew
function. De-asserting a pulse of duration greater than one clock will restart
the deskew initialization. Do NOT tie this pin to LOW. Please refer to the
Applications Information on the back for more information.
I
1
LVCMOS/LVTTL level input. This pin must be tied to logic High or Vcc to
enable DC Balance function(Figure 9). When tied low or left open, the DC
Balance function is disabled(Figure 8). Please refer to the Applications
Information on the back for more infomation.
I
1
Control Pin. This pin must be tied to logic High or Vcc.
I
6
Power supply pins for LVCMOS/LVTTL outputs and digital circuitry.
I
8
Ground pins for LVCMOS/LVTTL outputs and digital circuitry.
I
1
Power supply for PLL circuitry.
I
2
Ground pin for PLL circuitry.
I
2
Power supply pin for LVDS inputs.
I
3
Ground pins for LVDS inputs.
6
No Connect. Make NO Connection to these pins - leave open.
Note 10: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions
receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the cable inter-connects are disconnected which results in
floating/terminated inputs, the outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock output.
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