DS90CF582 Datasheet, PDF (6/12 Pages) National Semiconductor (TI) – LVDS 24-Bit Color Flat Panel Display (FPD) Link

AC Timing Diagrams
FIGURE 1 ‘‘WORST CASE’’ Test Pattern
TL F 12486 – 15
FIGURE 2 ‘‘16 GRAYSCALE’’ Test Pattern
TL F 12486 – 16
Note 1 The worst case test pattern produces a maximum toggling of digital circuits LVDS I O and CMOS TTL I O
Note 2 The 16 grayscale test pattern tests device power consumption for a ‘‘typical’’ LCD display pattern The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display
Note 3 Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN RxCLK OUT)
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