DS90CF582 Datasheet, PDF (11/12 Pages) National Semiconductor (TI) – LVDS 24-Bit Color Flat Panel Display (FPD) Link

DS90CF581 Pin Description FPD Link Transmitter
Pin Name
TxIN
I O No
I 28
TxOUTa
O4
TxOUTb
O4
FPSHIFT IN
I1
TxCLK OUTa O 1
TxCLK OUTb O 1
PWR DOWN
I1
V_CC
GND
I4
I5
PLL V_CC
PLL GND
I1
I2
LVDS V_CC
LVDS GND
I1
I3
Description
TTL level input This includes 8 Red 8 Green 8 Blue and 4 control lines (FPLINE FPFRAME
DRDY CNTL) (Also referred to as HSYNC VSYNC and DATA ENABLE)
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input The falling edge acts as data strobe
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input Assertion (low input) TRI-STATE the outputs ensuring low current at power down
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
DS90CF582 Pin Description FPD Link Receiver
Pin Name
RxINa
RxINb
RxOUT
I O No
I4
I4
O 28
RxCLK INa
I1
RxCLK INb
I1
FPSHIFT OUT O 1
PWR DOWN
I1
V_CC
GND
I4
I5
PLL V_CC
PLL GND
I1
I2
LVDS V_CC
LVDS GND
I1
I3
Description
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level data outputs This includes 8 Red 8 Green 8 Blue and 4 control lines (FPLINE
FPFRAME DRDY CNTL) (Also referred to as HSYNC VSYNC and DATA ENABLE)
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output The falling edge acts as data strobe
TTL level input Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply pin for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
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