DS90CF582 Datasheet, PDF (4/12 Pages) National Semiconductor (TI) – LVDS 24-Bit Color Flat Panel Display (FPD) Link

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TRANSMITTER SUPPLY CURRENT
I_CCTW
Transmitter Supply Current
Worst Case
I_CCTG
Transmitter Supply Current
16 Grayscale
I_CCTZ
Transmitter Supply Current
Power Down
RECEIVER SUPPLY CURRENT
I_CCRW
Receiver Supply Current
Worst Case
I_CCRG
Receiver Supply Current
16 Grayscale
I_CCRZ
Receiver Supply Current
Power Down
Conditions
R_L e 100X C_L e 5 pF
Worst Case Pattern (Figures 1 3)
R_L e 100X C_L e 5 pF
Grayscale Pattern (Figures 2 3)
Power Down e Low
C_L e 8 pF
Worst Case Pattern (Figures 1 4)
C_L e 8 pF
16 Grayscale Pattern (Figures 2 4)
Power Down e Low
Min Typ Max Units
f e 32 5 MHz
f e 37 5 MHz
f e 32 5 MHz
f e 37 5 MHz
34
46
mA
36
48
mA
27
42
mA
28
43
mA
1
10
mA
f e 32 5 MHz
f e 37 5 MHz
f e 32 5 MHz
f e 37 5 MHz
55
75
mA
60
80
mA
35
55
mA
37
58
mA
1
10
mA
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
CLHT
CHLT
TCIT
TCCS
TSSPW
RCCS
TCIP
TCIH
TCIL
TSTC
THTC
RCOP
Parameter
LVDS Low-to-High Transition Time (Figure 3)
LVDS High-to-Low Transition Time (Figure 3)
CMOS TTL Low-to-High Transition Time (Figure 4)
CMOS TTL High-to-Low Transition Time (Figure 4)
TxCLK IN Transition Time (Figure 5)
TxOUT Channel-to-Channel Skew (Note A) (Figure 6)
Tx Sub-Symbol Pulse Width (Figure 6)
f e 20 MHz
RxIN Channel-to-Channel Skew (Note B)
TxCLK IN Period (Figure 7)
TxCLK IN High Time (Figure 7)
TxCLK IN Low Time (Figure 7)
TxIN Setup to TxCLK IN (Figure 7)
TxIN Hold to TxCLK IN (Figure 7)
RxCLK OUT Period (Figure 8)
Min
55
25
0 35T
0 35T
8
25
25
Note A This limit based on bench characterization
Note B This limit assumes a maximum cable skew of 350 ps
Typ
0 75
0 75
35
27
7
T
0 5T
0 5T
2
T
Max
15
15
65
65
8
350
8
700
50
0 65T
0 65T
50
Units
ns
ns
ns
ns
ns
ps
ns
ps
ns
ns
ns
ns
ns
ns
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