DS90C387_06 Datasheet, PDF (6/26 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA

Receiver Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
RPLLS Receiver Phase Lock Loop Set (Figure 9)
RPDD
Receiver Powerdown Delay (Figure 11)
Max
Units
10
ms
1
µs
Chipset RSKM Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 4, 8). See Applications Infor-
mation section for more details on this parameter and how to apply it.
Symbol
Parameter
Min
Typ
Max
Units
RSKM
Receiver Skew Margin without
f = 112 MHz
170
ps
Deskew in non-DC Balance Mode, _{f = 100 MHz}
170
240
ps
(Figure 12), (Note 6)
f = 85MHz
300
350
ps
f = 66MHz
300
350
ps
RSKM
Receiver Skew Margin without
f = 112 MHz
170
ps
Deskew in DC Balance Mode,
f = 100 MHz
170
200
ps
(Figure 12), (Note 6)
f = 85 MHz
250
300
ps
f = 66 MHz
250
300
ps
f = 50MHz
100
350
ps
f = 40MHz
94
530
ps
RSKMD
RDR
Receiver Skew Margin with Deskew
in DC Balance, (Figure 13),
(Note 7)
Receiver Deskew Range
f = 40 to 80
MHz
f = 80 MHz
0.25TBIT
±1
ps
TBIT
RDSS
Receiver Deskew Step Size
f = 80 MHz
0.3 TBIT
ns
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional
performance.
Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of ±3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16). A jitter event of 3ns, represents worse case jump
in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
Note 6: Receiver Skew Margin (RSKM) is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse
positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew,
inter-symbol interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle, TJCC) + ISI (if any). See Applications Information section for more details.
Note 7: Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function will constrain the
receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This margin (RSKMD) allows for inter-symbol
interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and LVDS clock jitter (TJCC).
RSKMD ≥ ISI + TPPOS(variance) + source clock jitter (cycle to cycle). See Applications Information section for more details.
Note 8: Typical values for RSKM and RSKMD are applicable for fixed V_CC and T _A for the Transmitter and Receiver (both are assumed to be at the same V_CC and
T _A points).
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