DS90C387_06 Datasheet, PDF (19/26 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA

LVDS Interface (Continued)
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Note that the LVDS Clock signal is also DC Balanced in this mode. The rising edge location is fixed, but the location of the falling
edge will be in one of two locations as shown above. Optional features supported: Pre-emphasis, and Deskew.
FIGURE 18. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs
DC Balanced Mode - Data Enabled, BAL=High
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