DS90C387_06 Datasheet, PDF (14/26 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA

DS90CF388 Pin Descriptions — FPD Link Receiver
Pin Name
AnP
AnM
Rn, Gn, Bn,
DE, HSYNC,
VSYNC
RxCLK INP
RxCLK INM
RxCLK OUT
R_FDE
PLLSEL
BAL
DESKEW
PD
STOPCLK
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
CNTLE,
CNTLF
I/O
No.
Description
I
8
Positive LVDS differential data inputs.
I
8
Negative LVDS differential data inputs.
O
51
TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3
control lines — HSYNC (LP), VSYNC (FLM), DE (Data Enable).
I
1
Positive LVDS differential clock input.
I
1
Negative LVDS differential clock input.
O
1
TTL level clock output. The falling edge acts as data strobe.
I
1
Programmable control (DE) strobe select. Tied high for data active when DE
is high. (Note 12)
I
1
PLL range select. This pin must be tied to V_CC for auto-range. NC or tied to
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz. (Notes 13, 14)
I
1
Mode select for DC Balanced (new) or non-DC Balanced (backward
compatible) interface. BAL = LOW for non-DC Balanced mode. BAL = HIGH
for DC Balanced Mode (Auto-detect mode), with this pin HIGH the received
LVDS clock signal is used to determine if the interface is in new or backward
compatible mode. (Notes 12, 13, 15)
I
1
Deskew and oversampling “on/off” select. Deskew is active when input is
high. Only supported in DC Balance mode (BAL=High). To complete the
deskew operation, a minimum of four clock cycles is required during
blanking time. (Note 12)
I
1
TTL level input. When asserted (low input) the receiver data outputs are low
and clock output is high. (Note 12)
O
1
Indicates receiver clock input signal is not present with a logic high. With a
clock input present, a low logic is indicated.
I
6
Power supply pins for TTL outputs and digital circuitry.
I
8
Ground pins for TTL outputs and digital circuitry
I
1
Power supply for PLL circuitry.
I
2
Ground pin for PLL circuitry.
I
2
Power supply pin for LVDS inputs.
I
3
Ground pins for LVDS inputs.
O
2
TTL level data outputs. User-defined control signals - no connect when not
used.
Note 15: The DS90CF388 is designed to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90C387 and deserialize the LVDS
data according to the defined bit mapping.
10007308
FIGURE 16. Resistor Network for “DUAL” pin input - recommend using R1=R2=10kΩ for single to dual mode
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