DS90C387_06 Datasheet, PDF (22/26 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA

Applications Information (Continued)
plus the inverse of the calculated data disparity if the data is
sent inverted. The value of the running word disparity shall
saturate at +7 and −6.
The value of the DC Balance bit (DCBAL) shall be 0 when
the data is sent unmodified and 1 when the data is sent
inverted. To determine whether to send pixel data unmodi-
fied or inverted, the running word disparity and the current
data disparity are used. If the running word disparity is
positive and the current data disparity is positive, the pixel
data shall be sent inverted. If the running word disparity is
positive and the current data disparity is zero or negative, the
pixel data shall be sent unmodified. If the running word
disparity is negative and the current data disparity is positive,
the pixel data shall be sent unmodified. If the running word
disparity is negative and the current data disparity is zero or
negative, the pixel data shall be sent inverted. If the running
word disparity is zero, the pixel data shall be sent inverted.
Cable drive is enhanced with a user selectable pre-
emphasis feature that provides additional output current dur-
ing transitions to counteract cable loading effects. DC bal-
ancing on a cycle-to-cycle basis, is also provided to reduce
ISI (Inter-Symbol Interference). With pre-emphasis and DC
balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. These enhancements allow cables
5 to 10+ meters in length to be driven.
CONTROL SIGNAL SENT DURING BLANKING (DC
BALANCE MODE)
The data enable control signal (DE) is used in the DC
Balanced mode to distinguish between pixel data and control
information being sent. It must be continuously available to
the device in order to correctly separate pixel data from
control information. For this reason, DE shall be sent on the
clock signals, LVDS CLK1 and CLK2, when operating in the
DC Balanced mode. If the value of the control to be sent is 1
(active display), the value of the control word sent on the
clock signals shall be 1111000 or 1110000. If the value of the
control to be sent is 0 (blanking time), the value of the control
word sent on the clock signals shall be 1111100 or 1100000.
This is true when R_FDE=High. See also the pin description
tables.
The control information, such as HSYNC and VSYNC, is
always sent unmodified. The value of the control word to
send is determined by the running word disparity and the
value of the control to be sent. If the running word disparity is
positive and the value of the control to be sent is 0, the
control word sent shall be 1110000. If the running word
disparity is zero or negative and the control word to be sent
is 0, the control word sent shall be 1111000. If the running
word disparity is positive and the value of the control to be
sent is 1, the control word sent shall be 1100000. If the
running word disparity is zero or negative and the value of
the control to be sent is 1, the control word sent shall be
1111100. The DC Balance bit shall be sent as 0 when send-
ing control information during blanking time. See Figure 19.
RGB outputs on the DS90CF388 are forced LOW during the
blanking time.
Note that in the backward compatible mode (BAL=low) con-
trol and data is sent as regular LVDS data. See Figure 17.
SUPPORT OF CNTLE, CNTLF
The 387/388 will also support the transmission of one or two
additional user-defined control signals in the ’dual pixel’ DC
Balanced output mode which are active during blanking
while VSYNC is low. The additional control signals, referred
to as CNTLE and CNTLF, should be multiplexed with data
signals and provided to the transmitter inputs. Inputs B26 -
CNTLF and B27 - CNTLE are designated for this purpose.
When operating in ’DC Balanced’ mode, controls (CNTLE,
CNTLF) are transmitted on LVDS channels A4 and A5 during
the blanking interval when VSYNC is low. CNTLE and
CNTLF are sampled ONE (1) clock cycle after VSYNC tran-
sitions from a HIGH to a LOW state. CNTLE and CNTLF are
sampled on each cycle until VSYNC transitions from a LOW
to a HIGH, and they are then latched until the next VSYNC
LOW cycle. Refer to Table (Control Signals Transmitted
During Blanking) for details. These signals may be active
only during blanking while VSYNC is low. Control signal
levels are latched and held in the last valid state when
VSYNC transitions from low to high. These control signals
are available as TTL outputs on the receiver. CNTLE and
CNTLF outputs on the DS90CF388 should be left as a no
connect (NC) when not used.
Deskew
The OpenLDI receiver (DS90CF388) is able to tolerate a
minimum of 300ps skew between the signals arriving on a
single differential pair (intra-pair) and a minimum of ±1 LVDS
data bit time skew between signals arriving on dependent
differential pair (pair-to-pair). This is supported in the DC
Balance data transmission mode only. Each data channel is
deskewed independently and is tuned with a step size of 1/3
of a bit time over a range of +/−1 TBIT. The Deskew feature
operates up to clock rates of 80 MHz only. When using the
DESKEW feature, the sampling strobe will remain within the
middle third of the LVDS sub symbol.To complete the
deskew operation, a minimum of four clock cycles is required
during blanking time. This allows the chipset to support
reduced blanking applications.
Backwards Compatible Mode with FPD-Link
The transmitter provides a second LVDS output clock. Both
LVDS clocks will be identical in ’Dual pixel mode’. This
feature supports backward compatibility with the previous
generation of devices - the second clock allows the transmit-
ter to interface to panels using a ’dual pixel’ configuration of
two 24-bit or 18-bit ’notebook’ receivers.
Note that redundant copies of certain signals are also sent.
These signals are denoted with an * symbol, and are shown
in Figure 17. The DS90CF388 does not sample the bits
show with an * symbol. If interfaceing with FPD-Link Receiv-
ers, these signals may be recovered if desired.
Pre-emphasis feature is available for use in both the DC
Balanced and non-DC Balanced (backwards compatible)
modes.
Transmitter Features
The transmitter is designed to reject cycle-to-cycle jitter
which may be seen at the transmitter input clock. Very low
cycle-to-cycle jitter is passed on to the transmitter outputs.
Cycle-to-cycle jitter has been measured over frequency to
be less than 100 ps with input step function jitter applied.
This should be subtracted from the RSKM/RSKMD budget
as shown and described in Figure 12 and Figure 13. This
rejection capability significantly reduces the impact of jitter at
the TXinput clock pin, and improves the accuracy of data
sampling in the receiver. Transmitter output jitter is effected
by PLLVCC noise and input clock jitter - minimize supply
noise and use a low jitter clock source to limit output jitter.
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