DS90C387_06 Datasheet, PDF (23/26 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA

Applications Information (Continued)
Timing and control signals (VSYNC, HSYNC, DE and two
user-defined signals) are sent during blanking intervals to
guarantee correct reception of these critical signals.
The transmitter is offered with programmable edge data
strobes for convenient interface with a variety of graphics
controllers. The transmitter can be programmed for rising
edge strobe or falling edge strobe through a dedicated pin. A
rising edge transmitter will inter-operate with a falling edge
receiver without any translation logic.
RSKM - Receiver Skew Margin
RSKM is a chipset parameter and is explained in AN-1059 in
detail. It is the difference between the transmitter’s pulse
position and the receiver’s strobe window. RSKM must be
greater than the summation of: Interconnect skew, LVDS
Source Clock Jitter (TJCC), and ISI (if any). See Figure 12.
Interconnect skew includes PCB traces differences, connec-
tor skew and cable skew for a cable application. PCB trace
and connector skew can be compensated for in the design of
the system. Cable skew is media type and length dependant.
RSKMD - Receiver Skew Margin with DESKEW
RSKMD is a chipset parameter and is applicable when the
DESKEW feature of the DS90CF388 is employed. It is the
DS90C387A/DS90CF388A
The DS90C387/CF388 chipset is electrically similar to the
DS90C387A/CF388A. The DS90C387A/CF388A is recom-
mended if support of longer cable drive is not required. DC
Balance data transmission and cable deskew features are
Configuration Table
difference between the receiver’s strobe window and the
ideal pulse locations. The DESKEW feature adjusts for skew
between each data channel and the clock channel. This
feature is supported up to 80 MHz clock rate. RSKMD must
be greater than the summation of: Transmitter’s Pulse Posi-
tion variance, LVDS Source Clock Jitter (TJCC), and ISI (if
any). See Figure 12. With Deskew, RSKMD is ≥ 25% of
TBIT. Deskew compensates for interconnect skew which
includes PCB traces differences, connector skew and cable
skew (for a cable application). PCB trace and connector
skew can be compensated for in the design of the system.
Note, cable skew is media type and length dependant. Cable
length may be limited by the RSKMD parameter prior to the
interconnect skew reaching 1 TBIT in length due to ISI
effects.
POWER DOWN
Both transmitter and receiver provide a power down feature.
When asserted current draw through the supply pins is
minimized and the PLLs are shut down. The transmitter
outputs are in TRI-STATE when in power down mode. The
receiver outputs are forced to a active LOW state when in
the power down mode. (See Pin Description Tables). The PD
pin should be driven HIGH to enable the device once V_CC is
stable.
disabled to minimize overall power dissipation. The devices
will also directly inter-operate with existing FPD-Link devices
for backward compatibility.
Pin
R_FB (Tx only)
R_FDE (both Tx and Rx)
BAL (both Tx and Rx)
DUAL (Tx only)
TABLE 7. TRANSMITTER / RECEIVER CONFIGURATION TABLE
Condition
R_FB = V_CC
R_FB = GND
R_FDE = V_CC
R_FDE = GND
BAL=V_CC
BAL=Gnd
DUAL=V_CC
DUAL=1/2V_CC
DUAL=Gnd
Configuration
Rising Edge Data Strobe
Falling Edge Data Strobe
Active data DE = High
Active data DE = Low
DC Balanced enabled
DC Balanced disabled (backward compatible to FPD-Link)
48-bit color (dual pixel) support
Single-to-dual support
24-bit color (single pixel) support
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