DS90C387A Datasheet, PDF (6/19 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface / FPD-Link

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out
1.52
2.0
ns
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out
0.5
1.0
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out
1.7
2.0
ns
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out
0.5
1.0
ns
RCOP
RxCLK OUT Period (Figure 7)
8.928
T
30.77
ns
RCOH
RxCLK OUT High Time (Figure 7)(Note 4)
f = 112 MHz
3.5
ns
f = 85 MHz
4.5
ns
RCOL
RxCLK OUT Low Time (Figure 7)(Note 4)
f = 112 MHz
3.5
ns
f = 85 MHz
4.5
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 7)(Note 4) f = 112 MHz
2.4
ns
f = 85 MHz
3.0
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 7)(Note 4) f = 112 MHz
3.4
ns
f = 85 MHz
4.75
ns
RPLLS Receiver Phase Lock Loop Set (Figure 9)
10
ms
RPDD
Receiver Powerdown Delay (Figure 11)
1
µs
RSKM
Receiver Skew Margin (Figure 12) (Notes 4, 6), f = 112 MHz
170
ps
f = 100 MHz
170
240
ps
f = 85MHz
300
350
ps
f = 66MHz
300
350
ps
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested at 112MHz to verify
functional performance.
Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of ±3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16). A jitter event of 3ns, represents worse case jump
in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
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