DS90C387A Datasheet, PDF (14/19 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface / FPD-Link

LVDS Interface / TFT Data (Color) Mapping
Different color mapping options exist. See National Applica-
tion Notes 1127 and 1163 for details.
The LVDS Clock waveshape is shown in Figure 15. Note that
the rising edge of the LVDS clock occurs two LVDS sub
symbols before the current cycle of data. The clock is com-
pose of a 4 LVDS sub symbol HIGH time and a 3 LVDS sub
symbol LOW time. The respective pin (transmitter and re-
ceiver) names are show in Figure 15. As stated above these
names are not the color mapping information (MSB/LSB) but
pin names only.
Inputs B17 and B27 are double wide bits. If using the
DS90CF388A, this bits are sampled in the back half of the bit
only. Also, the DE signal is mapped to two LVDS sub sym-
bols. The DS90CF388A only samples the DE bit on channel
A2. Two FPD-Link receivers may also be used in place of the
DS90CF388A, since the DS90C387A provides two LVDS
clocks. If this is the case, the FPD-Link receiver datasheet
needs to be consulted for recovery mapping information. In
this application, it is possible to recover two signals of: DE,
B17 and B27 from the transmitter.
There are two reserved bits (RES). The DS90CF388A ig-
nores these bits. If using separate FPD-Link receivers, the
corresponding receiver outputs for these two bits should be
left open (NC).
FIGURE 15. TTL Data Inputs Mapped to LVDS Outputs 387A/388A
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