DS90C387A Datasheet, PDF (13/19 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface / FPD-Link

DS90CF388A Pin Description — FPD Link Receiver
Pin Name
AnP
AnM
Rn, Gn, Bn,
DE, HSYNC,
VSYNC
RxCLK INP
RxCLK INM
RxCLK OUT
R_FDE
PLLSEL
PD
STOPCLK
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
CNTLE,
CNTLF
I/O
No.
Description
I
8
Positive LVDS differential data inputs.
I
8
Negative LVDS differential data inputs.
O
51
TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3
control lines — HSYNC (LP), VSYNC (FLM), DE (Data Enable).
I
1
Positive LVDS differential clock input.
I
1
Negative LVDS differential clock input.
O
1
TTL level clock output. The falling edge acts as data strobe.
I
1
Programmable control (DE) strobe select. Tied high for data active when DE
is high. (Note 10)
I
1
PLL range select. This pin must be tied to V_CC for auto-range. NC or tied to
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz. (Notes 10, 11)
I
1
TTL level input. When asserted (low input) the receiver data outputs are low
and clock output is high. (Note 10)
O
1
Indicates receiver clock input signal is not present with a logic high. With a
clock input present, a low logic is indicated.
I
6
Power supply pins for TTL outputs and digital circuitry.
I
10
Ground pins for TTL outputs and digital circuitry
I
1
Power supply for PLL circuitry.
I
2
Ground pin for PLL circuitry.
I
2
Power supply pin for LVDS inputs.
I
3
Ground pins for LVDS inputs.
2
No Connect. Make NO Connection to these pins - leave these pins open, do
not tie to ground or V_CC.
Note 12: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions
receiver inputs will be in a HIGH state. If the clock input is floating/terminated, outputs will remain in the last valid state.
13
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