DS90C387A Datasheet, PDF(15/19 Page) National Semiconductor (TI) – Dual Pixel LVDS Display Interface / FPD-Link

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DS90C387A Datasheet, PDF (15/19 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface / FPD-Link

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Applications Information

How to configure the DS90C387A and DS90CF388A for

most common application:

1. To configure for single input pixel-to-dual pixel output

application, the DS90C387 âDUALâ pin must be set to 1/2

Vcc=1.65V. This may be implemented using pull-up and

pull-down resistors of 10kâ¦. In this configuration, the input

signals (single pixel) are split into odd and even pixel (dual

pixels) starting with the odd (first) pixel outputs A0-to-A3 the

next even (second) pixel outputs to A4-to-A7. The splitting of

the data signal also starts with DE (data enable) transitioning

from logic low to high indicating active data. The âR_FDEâ pin

must be set high in this case. The number of clock cycles

during blanking must be an EVEN number. This configura-

tion will allow the user to interface to an LDI receiver

(DS90CF388A) or to two FPD-Link ânotebookâ receivers

(DS90CF384A or DS90CF386).

2. To configure for single pixel or dual pixel application using

the DS90C387A/DS90CF388A, the âDUALâ pin must be set

to Vcc (dual) or Gnd (single). In dual mode, the

transmitter-DS90C387A has two LVDS clock outputs en-

abling an interface to two FPD-Link ânotebookâ receivers

(DS90CF384A or DS90CF386). In single mode, outputs

A4-to-A7 and CLK2 are disabled which reduces power dis-

sipation.

The DS90CF388A is able to support single or dual pixel

interface up to 112MHz operating frequency. This receiver

may also be used to interface to a VGA controller with an

integrated LVDS transmitter.

Transmitter Features:

The transmitter is designed to reject cycle-to-cycle jitter

which may be seen at the transmitter input clock. Very low

cycle-to-cycle jitter is passed on to the transmitter outputs.

This significantly reduces the impact of jitter provided by the

input clock source, and improves the accuracy of data sam-

pling.

The transmitter is offered with programmable edge data

strobes for convenient interface with a variety of graphics

controllers. The transmitter can be programmed for rising

edge strobe or falling edge strobe through a dedicated pin. A

rising edge transmitter will inter-operate with a falling edge

receiver without any translation logic.

Pre-Emphasis:

Pre-Emphasis adds extra current during LVDS logic transi-

tion to reduce the cable loading effects. Pre-emphasis

strength is set via a DC voltage level applied from min to max

(0.75V to Vcc) at the âPREâ pin. A higher input voltage on the

âPREâ pin increases the magnitude of dynamic current dur-

ing data transition. The âPREâ pin requires one pull-up resis-

tor (Rpre) to Vcc in order to set the DC level. There is an

internal resistor network, which cause a voltage drop. Please

refer to the tables below to set the voltage level.

TABLE 1. Pre-emphasis DC voltage level with (Rpre)

Rpre

1Mâ¦ or NC

50kâ¦

9kâ¦

3kâ¦

1kâ¦

100â¦

Resulting PRE Voltage

0.75V

1.0V

1.5V

2.0V

2.6V

Vcc

Effects

Standard LVDS

50% pre-emphasis

100% pre-emphasis

TABLE 2. Pre-emphasis needed per cable length

Frequency

112MHz

80MHz

65MHz

56MHz

PRE Voltage

1.0V

1.5V

1.0V

1.2V

1.5V

1.0V

Typical cable length

2 meters

5 meters

2 meters

7 meters

10 meters

Note 13: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating

frequency.

RSKM - Receiver Skew Margin

RSKM is a chipset parameter and is explained in AN-1059 in

detail. It is the difference between the transmitterâs pulse

position and the receiverâs strobe window. RSKM must be

greater than the summation of: Interconnect skew, LVDS

Source Clock Jitter (TJCC), and ISI (if any). See Figure 12.

Interconnect skew includes PCB traces differences, connec-

tor skew and cable skew for a cable application. PCB trace

and connector skew can be compensated for in the design of

the system. Cable skew is media type and length dependant.

Power Down:

Both transmitter and receiver provide a power down feature.

When asserted current draw through the supply pins is

minimized and the PLLs are shut down. The transmitter

outputs are in TRI-STATE when in power down mode. The

receiver outputs are forced to a active LOW state when in

the power down mode. (See Pin Description Tables). The PD

pin should be driven HIGH to enable the device once VCC is

stable.

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