DS90C387A Datasheet, PDF (5/19 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface / FPD-Link

Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
TCIT
TxCLK IN Transition Time (Figure 5)
DUAL=Gnd or Vcc
1.0
2.0
DUAL=1/2Vcc
1.0
1.5
TCIP
TxCLK IN Period (Figure 6)
DUAL=Gnd or Vcc
8.928
T
DUAL=1/2Vcc
5.88
TCIH
TxCLK in High Time (Figure 6)
0.35T
0.5T
TCIL
TxCLK in Low Time (Figure 6)
0.35T
0.5T
TXIT
TxIN Transition Time
1.5
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V
(disabled)
LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max)
LHLT
LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V
(disabled)
LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max)
TBIT
Transmitter Output Bit Width
DUAL=Gnd or Vcc
DUAL=1/2Vcc
TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70 MHz
−250
f = 70 to 112 MHz
−200
TCCS
TxOUT Channel to Channel Skew
TSTC
TxIN Setup to TxCLK IN (Figure 6)
2.7
THTC
TxIN Hold to TxCLK IN (Figure 6)
0
TJCC
Transmitter Jitter Cycle-to-cycle (Figures
13, 14) (Note 5), DUAL=Vcc
f = 112 MHz
f = 85 MHz
f = 65 MHz
f = 56 MHz
f = 32.5 MHz
TPLLS Transmitter Phase Lock Loop Set (Figure 8)
TPDD
Transmitter Powerdown Delay (Figure 10)
Typ
0.14
0.11
0.16
0.11
1/7 TCIP
2/7 TCIP
0
0
100
85
60
70
100
75
Max
3.0
1.7
30.77
15.38
0.65T
0.65T
6.0
Max
0.7
0.6
0.8
0.7
+250
+200
100
75
80
120
110
10
100
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ns
ps
ps
ps
ps
ps
ms
ns
5
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