DS64EV400 Datasheet, PDF (6/18 Pages) National Semiconductor (TI) – Programmable Quad Equalizer

Symbol
Parameter
Conditions
Min
Typ
Max
(note 2)
SIGNAL DETECT and ENABLE TIMING
t_ZISD
Input OFF to ON detect — SD Response time measurement at
Output High Response Time
V_IN to SD output, V_IN = 800 mV_P-P,
35
t_IZSD
Input ON to OFF detect — SD ^{100 Mbps, 40” of 6 mil microstrip}
Output Low Response Time
FR4
400
(Figure 1, 4), (Note 7)
t_OZOED
EN High to Output ON Response Response time measurement at
Time
EN input to V_O, V_IN = 800 mV_P-P,
150
t_ZOED
EN Low to Output OFF Response ^{100 Mbps, 40” of 6 mil microstrip}
Time
FR4
5
(Figure 1, 5), (Note 7)
Units
ns
ns
ns
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at V_DD = 3.3V or 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mV_P-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 7: Measured with clock-like {11111 00000} pattern.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (J_OUT2 – J_IN2). J_OUT is the random jitter at equalizer outputs in ps-rms, see point C of Figure
1; J_IN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
Note 9: The V_DD2.5 is V_DD = 2.5V ± 5% and V_DD3.3 is V_DD = 3.3V ± 10%.
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