DS64EV400 Datasheet, PDF (2/18 Pages) National Semiconductor (TI) – Programmable Quad Equalizer

Pin Descriptions
Pin Name Pin #
I/O, Type
HIGH SPEED DIFFERENTIAL I/O
IN_0+
1
I, CML
IN_0–
2
IN_1+
IN_1–
4
I, CML
5
IN_2+
IN_2–
8
I, CML
9
IN_3+
IN_3–
11
I, CML
12
OUT_0+
OUT_0–
36
O, CML
35
OUT_1+
OUT_1–
33
O, CML
32
OUT_2+
OUT_2–
29
O, CML
28
OUT_3+
OUT_3–
26
O, CML
25
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
37
I, LVCMOS
14
23
DEVICE CONTROL
EN0
44
I, LVCMOS
EN1
42
I, LVCMOS
EN2
40
I, LVCMOS
EN3
38
I, LVCMOS
FEB
21
I, LVCMOS
SD0
SD1
SD2
SD3
POWER
V_DD
GND
DAP
45
O, LVCMOS
43
O, LVCMOS
41
O, LVCMOS
39
O, LVCMOS
3, 6, 7,
10, 13,
15, 46
22, 24,
27, 30,
31, 34
PAD
Power
Power
Power
Description
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to V_DD and OUT_0- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to V_DD and OUT_1- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to V_DD and OUT_2- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to V_DD and OUT_3- to V_DD.
BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is
internally pulled high. BST_1 and BST_0 are internally pulled low.
Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]
pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register
bits. FEB is internally pulled High.
Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
V_DD = 2.5V ± 5% or 3.3V ± 10%. V_DD pins should be tied to V_DD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each V_DD pin to GND planes.
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
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