DS64EV400 Datasheet, PDF (12/18 Pages) National Semiconductor (TI) – Programmable Quad Equalizer

DS64EV400 Functional
Descriptions
The DS64EV400 is a programmable quad equalizer opti-
mized for operation up to 10 Gbps for backplane and cable
applications.
DATA CHANNELS
The DS64EV400 provides four data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a CML driver as shown in Fig-
ure 8.
FIGURE 8. Simplified Block Diagram
30032006
EQUALIZER BOOST CONTROL
Each data channel support eight programmable levels of
equalization boost. The state of the FEB pin determines how
the boost settings are controlled. If the FEB pin is held High,
then the equalizer boost setting is controlled by the Boost Set
pins (BST_[2:0]) in accordance with Table 2. If this program-
ming method is chosen, then the boost setting selected on the
Boost Set pins is applied to all channels. When the FEB pin
is held Low, the equalizer boost level is controlled through the
SMBus. This programming method is accessed via the ap-
propriate SMBus registers (see Table 1). Using this approach,
equalizer boost settings can be programmed for each channel
individually. FEB is internally pulled High (default setting);
therefore if left unconnected, the boost settings are controlled
by the Boost Set pins (BST_[0:2]). The eight levels of boost
settings enables the DS64EV400 to address a wide range of
media loss and data rates.
TABLE 2. EQ Boost Control Table
6 mil
Microstri
p FR4
Trace
Length
(m)
24 AWG
Twin-AX
cable
length (m)
Channel
Loss at
3.2 GHz
(dB)
Channel
Loss at 5
GHz (dB)
BST_N
[2, 1, 0]
0
0
0
0
000
5
2
5
6
001
10
3
7.5
10
010
15
4
10
14
011
20
5
12.5
18
100
(Default)
25
6
15
21
101
30
7
17
24
110
40
10
22
30
111
DEVICE STATE AND ENABLE CONTROL
The DS64EV400 has an enable feature on each data channel
which provides the ability to control device power consump-
tion. This feature can be controlled either an Enable Pin
(EN_n) with Reg 07 = 00'h (default value), or by the Enable
Control Bit register which can be configured through the SM-
Bus port (see Table 1 and Table 3 for detail register informa-
tion), which require setting Reg 07 = 01'h and changing
register value of Reg 03, 04. If the Enable is activated using
either the external EN_n pin or SMBUS register, the corre-
sponding data channel is placed in the ACTIVE state and all
device blocks function as described. The DS64EV400 can al-
so be placed in STANDBY mode to save power. In the
STANDBY mode only the control interface including the SM-
Bus port, as well as the signal detection circuit remain active.
TABLE 3. Controlling Device State
Register 07[0] ENn Pin
(SMBus) (CMOS)
CH 0:
Reg. 03 bit 3
CH 1:
Reg. 03 bit 7
CH 2:
Reg. 04 bit 3
CH 3:
Reg. 04 bit 7
(EN Control)
Device State
0 : Disable
1
X
ACTIVE
0 : Disable
0
X
STANDBY
1 : Enable
X
0
ACTIVE
1 : Enable
X
1
STANDBY
SIGNAL DETECT
The DS64EV400 features a signal detect circuit on each data
channel. The status of the signal of each channel can be de-
termined by either reading the Signal Detect bit (SDn) in the
SMBus registers (see Table 1) or by the state of each SDn
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