DS64EV400 Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – Programmable Quad Equalizer

Pin Name Pin #
I/O, Type
Description
SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS
SDA
18 I/O, LVCMOS Data input/output (bi-directional). Internally pulled high.
SDC
17
I, LVCMOS Clock input. Internally pulled high.
CS
16
I, LVCMOS Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When
pulled low, access to the equalizer SMBus registers are disabled. Please refer to “SMBus
configuration Registers” section for detail information.
Other
Reserv
19, 20
Reserved. Do not connect.
47,48
Note: I = Input O = Output
Connection Diagram
Ordering Information
NSID
DS64EV400SQ
DS64EV400SQX
Package Type, Qty Size
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 250
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 2500
30032026
Package ID
SQA48D
SQA48D
3
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