DS16EV5110 Datasheet, PDF (6/16 Pages) –

Symbol
RJ
Parameter
Random Jitter
BIT RATE
F_CLK
BR
Clock Frequency
Bit Rate
(Note 7)
(Note 8)
Conditions
Clock Path
(Note 5)
Clock Path
(Note 5)
Min
Typ
Max
Units
3
psrms
25
165
MHz
0.25
1.65
Gbps
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: Typical values represent most likely parametric norms at V_DD = 3.3V, T_A = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mV_P-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (TPC of Figure 1), minus the deterministic jitter before the test channel (TPA of Figure 1). Random
jitter is removed through the use of averaging or similar means.
Note 7: Total Jitter is defined as peak-to-peak deterministic jitter from (Note 8) + 14.2 times random jitter.
Note 8: Random jitter contributed by the equalizer is defined as sq rt (J_OUT2 − J_IN2). J_OUT is the random jitter at equalizer outputs in ps-rms, see TPC of Figure
1; J_IN is the random jitter at the input of the equalizer in ps-rms, see TPA of Figure 1.
Electrical Characteristics — Serial Bus Interface (Notes 2, 3)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Serial Bus Interface — DC Specifications
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.8
I_PULLUP
Current through pull-up resistor or
4
current source
I_PULLUP
Current through pull-up resistor or
4
current source
V_DD
Nominal Bus Voltage
3.0
I_LEAK-Bus
Input Leakage per bus segment (Note 9)
I_LEAK-Pin
Input Leakage per device pin
C_I
Capacitance for SDA and SDC (Note 9)
(Note 10)
R_TERM
Termination Resistance
V_DD3.3
(Note 9)
(Note 10)
(Note 11)
V_DD2.5
(Note 9)
(Note 10)
(Note 11)
Serial Bus Interface Timing Specification
FSMB
Bus Operating Frequency
(Note 12)
10
TBUF
Bus Free Time Between Stop and
4.7
Start Condition
THD:STA
Hold Time After (Repeated) Start At I_PULLUP, Max
Condition. First CLK generated
4.0
after this period.
TSU:STA
Repeated Start Condition Setup
4.7
Time
Typ
2000
1000
Max
0.8
V_DD
3.6
±200
±10
10
100
Units
V
V
mA
mA
V
µA
µA
pF
Ω
Ω
kHz
µS
µS
µS
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