DS16EV5110 Datasheet, PDF (11/16 Pages) –

CLOCK CHANNEL SIGNAL DETECT
The DS16EV5110 features a signal detect circuit on the clock
channel. The status of the clock signal can be determined by
either reading the Signal Detect bit (SD) in the SMBus regis-
ters (see Table 1) or by the state of the SD pin. A logical high
indicates the presence of a signal that has exceeded a spec-
ified maximum threshold value (called SD_ON). A logical low
means that the clock signal has fallen below a minimum
threshold value (called SD_OFF). These values are pro-
grammed via the SMBus (Table 1). If not programmed via the
SMBus, the minimum and maximum thresholds take on the
default values for the minimum and maximum values as indi-
cated in Table 4. The Signal Detect threshold values can be
changed through the SMBus.
TABLE 4. Clock Channel Signal Detect Threshold Values
Bit 1 Bit 0 Minimum Threshold Maximum Threshold
— Register 06 (mV) — Register 05 (mV)
00
30 (Default)
100 (Default)
01
10
60
10
60
160
11
40
120
OUTPUT LEVEL CONTROL
The output amplitude of the TDMS drivers for both the data
channels and the clock channel can be controlled via the SM-
Bus (see Table 1). The default output level is TBD mV p-p.
The following Table presents the output level values support-
ed:
TABLE 5. Output Level Control Settings
Bit 3
Bit 2
Output Level (mV)
0
0
TBD
0
1
TBD
1
0
TBD
1
1
TBD
AUTOMATIC ENABLE FEATURE
It may be desired for the DS16EV5110 to be configured to
automatically enter STANDBY mode if no clock signal is
present. This is implemented by connecting the Signal Detect
(SD) pin to the external (CMOS) Enable (EN) pin. In order for
this option to function properly, the FEB pin must be either
tied high or not connected (the FEB pin is internally pulled
high by default). If the clock signal applied to the clock channel
input swings above the maximum level specified in the thresh-
old register via the SMBus, then the SD pin is asserted high.
If the SD pin is connected to the EN pin, this will enable the
equalizer, limiting amplifier, and output buffer on the data
channels as well as the limiting amplifier and output buffer on
the clock channel (provided that the FEB pin is high); thus the
DS16EV5110 will automatically enter the ACTIVE state. If the
clock signal present falls below the minimum level specified
in the threshold register, then the SD pin will be asserted low,
causing the aforementioned blocks to be placed in the
STANDBY state.
Application Information
The DS16EV5110 is used to recondition DVI/HDMI video sig-
nals or differential signals with similar characteristics after
signal loss and degradation due to transmission through a
length of shielded or unshielded cable.
FIGURE 4. DS16EV5110 Typical Use
20216239
DVI 1.0 ANDHDMI V1.2A APPLICATIONS
A single DS16EV5110 can be used to implement cable ex-
tension solutions with various resolutions and screen refresh
rates. The range of digital serial rates supported is between
250 Mbps and 1.65 Gbps. For applications requiring ultra-
high resolution for DVI applications (e.g., QXGA and WQX-
GA), a “dual link” TMDS interface is required. This is easily
configured by using two DS16EV5110 devices as shown in
Figure 5.
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