DS90CR287_04 Datasheet, PDF (5/16 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3)
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3)
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 15)
f = 85 MHz
RSPos1 Receiver Input Strobe Position for Bit 1
RSPos2 Receiver Input Strobe Position for Bit 2
RSPos3 Receiver Input Strobe Position for Bit 3
RSPos4 Receiver Input Strobe Position for Bit 4
RSPos5 Receiver Input Strobe Position for Bit 5
RSPos6 Receiver Input Strobe Position for Bit 6
RSKM
RxIN Skew Margin (Note 5) (Figure 16)
f = 85 MHz
RCOP
RxCLK OUT Period (Figure 6)
RCOH
RxCLK OUT High Time (Figure 6)
f = 85 MHz
RCOL
RxCLK OUT Low Time (Figure 6)
RSRC
RxOUT Setup to RxCLK OUT (Figure 6)
RHRC
RxOUT Hold to RxCLK OUT (Figure 6)
RCCD
RPLLS
RxCLK IN to RxCLK OUT Delay @ 25˚C, V_CC = 3.3V (Note 6)(Figure 8)
Receiver Phase Lock Loop Set (Figure 10)
RPDD
Receiver Powerdown Delay (Figure 13)
Min
0.49
2.17
3.85
5.53
7.21
8.89
10.57
290
11.76
4
3.5
3.5
3.5
5.5
Typ
2
1.8
0.84
2.52
4.20
5.88
7.56
9.24
10.92
T
5
5
7
Max
3.5
3.5
1.19
2.87
4.55
6.23
7.91
9.59
11.27
50
6.5
6
9.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
µs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and source clock (less than 150 ps).
Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
10108702
5
www.national.com