DS90CR287_04 Datasheet, PDF (1/16 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz

July 2004
DS90CR287/DS90CR288A
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-85 MHz
General Description
The DS90CR287 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit-
ted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CR288A receiver con-
verts the four LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency of 85
MHz, 28 bits of TTL data are transmitted at a rate of 595
Mbps per LVDS data channel. Using a 85 MHz clock, the
data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Features
n 20 to 85 MHz shift clock support
n 50% duty cycle on receiver output clock
n 2.5 / 0 ns Set & Hold Times on TxINPUTs
n Low power consumption
n ±1V common-mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 2.38 Gbps throughput
n Up to 297.5 Mbytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead TSSOP package
Block Diagrams
DS90CR287
DS90CR288A
Order Number DS90CR287MTD
See NS Package Number MTD56
10108701
Order Number DS90CR288AMTD
See NS Package Number MTD56
10108727
© 2004 National Semiconductor Corporation DS101087
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