DS90CR287_04 Datasheet, PDF (4/16 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
I_CCTW
Transmitter Supply Current Worst
Case (with Loads)
R_L = 100Ω,
C_L = 5 pF,
Worst Case
Pattern
(Figures 1, 2)
f = 33 MHz
f = 40 MHz
f = 66 MHz
f = 85 MHz
31
45
mA
32
50
mA
37
55
mA
42
60
mA
I_CCTZ
Transmitter Supply Current Power
Down
PWR DWN = Low
Driver Outputs in TRI-STATE
under Powerdown Mode
10
55
µA
RECEIVER SUPPLY CURRENT
I_CCRW
Receiver Supply Current Worst
Case
C_L = 8 pF,
Worst Case
Pattern
(Figures 1, 3)
f = 33 MHz
f = 40 MHz
f = 66 MHz
f = 85 MHz
49
70
mA
53
75
mA
81
114
mA
96
135
mA
I_CCRZ
Receiver Supply Current Power
Down
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
140 400
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ∆V_OD).
Note 4: V_OS previously referred as V_CM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
LLHT
LVDS Low-to-High Transition Time (Figure 2)
LHLT
LVDS High-to-Low Transition Time (Figure 2)
TCIT
TxCLK IN Transition Time (Figure 4)
TPPos0 Transmitter Output Pulse Position for Bit0 (Figure 14)
f = 85 MHz
TPPos1 Transmitter Output Pulse Position for Bit1
TPPos2 Transmitter Output Pulse Position for Bit2
TPPos3 Transmitter Output Pulse Position for Bit3
TPPos4 Transmitter Output Pulse Position for Bit4
TPPos5 Transmitter Output Pulse Position for Bit5
TPPos6 Transmitter Output Pulse Position for Bit6
TCIP
TxCLK IN Period (Figure 5 )
TCIH
TxCLK IN High Time (Figure 5)
TCIL
TxCLK IN Low Time (Figure 5)
TSTC
TxIN Setup to TxCLK IN (Figure 5)
f = 85 MHz
THTC
TxIN Hold to TxCLK IN (Figure 5)
TCCD
TPLLS
TxCLK IN to TxCLK OUT Delay (Figure 7)
Transmitter Phase Lock Loop Set (Figure 9)
T_A = 25˚C,
V_CC = 3.3V
TPDD
Transmitter Powerdown Delay (Figure 12)
TJIT
TxCLK IN Cycle-to-Cycle Jitter (Input clock requirement)
Min
1.0
−0.20
1.48
3.16
4.84
6.52
8.20
9.88
11.76
0.35T
0.35T
2.5
0
3.8
Typ
0.75
0.75
0
1.68
3.36
5.04
6.72
8.40
10.08
T
0.5T
0.5T
Max
1.5
1.5
6.0
0.20
1.88
3.56
5.24
6.92
8.60
10.28
50
0.65T
0.65T
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.3
ns
10
ms
100
ns
2
ns
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