COP87L88KG Datasheet, PDF (5/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with UART and Three Multi-Function Timers

AC Electrical Characteristics COP888KG b40 C ^s T_A ^s a85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t_c)
Crystal Resonator
R C Oscillator
4 5V ^s V_CC ^s 5 5V
25
2 7V ^s V_CC ^k 4 5V
10
4 5V ^s V_CC ^s 5 5V
75
2 7V ^s V_CC ^k 4 5V
30
Inputs
t_SETUP
t_HOLD
4 5V ^s V_CC ^s 5 5V
200
2 7V ^s V_CC ^k 4 5V
500
4 5V ^s V_CC ^s 5 5V
60
2 7V ^s V_CC ^k 4 5V
150
Output Propagation Delay
t_PD1 t_PD0
SO SK
All Others
R_L e 2 2k C_L e 100 pF
4 5V ^s V_CC ^s 5 5V
2 7V ^s V_CC ^k 4 5V
4 5V ^s V_CC ^s 5 5V
2 7V ^s V_CC ^k 4 5V
MICROWIRE Setup Time (t_UWS) (Note 5)
V_CC ^t 4 5V
20
MICROWIRE Hold Time (t_UWH) (Note 5)
V_CC ^t 4 5V
56
MICROWIRE Output Propagation Delay (t_UPD)
V_CC ^t 4 5V
Input Pulse Width (Note 6)
Interrupt Input High Time
1
Interrupt Input Low Time
1
Timer 1 2 3 Input High Time
1
Timer 1 2 3 Input Low Time
1
Reset Pulse Width
1
DC
ms
DC
ms
DC
ms
DC
ms
ns
ns
ns
ns
07
ms
1 75
ms
1
ms
25
ms
ns
ns
220
ns
t_c
t_c
t_c
t_c
ms
Note 1 Maximum rate of voltage change must be less than 0 5 V ms
Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open
Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Measurement of IDD HALT is done with device neither sourcing or
sinking current with L C and G0–G5 programmed as low outputs and not driving a load all outputs programmed low and not driving a load all inputs tied to V_CC
clock monitor and comparators disabled Parameter refers to HALT mode entered via setting bit 7 of the G Port data register Part will pull up CKI during HALT in
crystal clock mode
Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages greater than V_CC and the pins will have sink current to
V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC) The effective resistance to V_CC is 750X
(typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V WARNING Voltages in excess of 14V will cause damage to
the pins This warning excludes ESD transients
Note 5 Parameter characterized but not tested
Note 6 t_c Instruction Cycle Time
5
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