COP87L88KG Datasheet, PDF (10/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with UART and Three Multi-Function Timers

Reset
The RESET input when pulled low initializes the microcon-
troller Initialization will occur whenever the RESET input is
pulled low Upon initialization the data and configuration
registers for ports L G and C are cleared resulting in these
Ports being initialized to the TRI-STATE mode Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and or Clock Monitor error
output pin Port D is set high The PC PSW ICNTRL
CNTRL T2CNTRL and T3CNTRL control registers are
cleared The UART registers PSR ENU (except that TBMT
bit is set) ENUR and ENUI are cleared The Comparator
Select Register is cleared The S register is initialized to
zero The Multi-Input Wakeup registers WKEN and WKEDG
are cleared Wakeup register WKPND is unknown The
stack pointer SP is initialized to 6F hex
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed with the
WATCHDOG service window bits set and the Clock Monitor
bit set The WATCHDOG and Clock Monitor circuits are in-
hibited during reset The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t_C clock cycles The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset A Clock Monitor error
will cause an active low error output on pin G1 This error
output will continue until 16 t_C – 32 t_C clock cycles following
the clock frequency reaching the minimum specified value
at which time the G1 output will enter the TRI-STATE mode
The external RC network shown in Figure 6 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes
RC l 5 c Power Supply Rise Time
TL DD12864–7
FIGURE 6 Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz The CKO output
clock is on pin G7 (crystal configuration) The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (1 t_c)
Figure 7 shows the Crystal and R C oscillator diagrams
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator
Table A shows the component values required for various
standard crystal values
R C OSCILLATOR
By selecting CKI as a single pin oscillator input a single pin
R C oscillator circuit can be connected to it CKO is avail-
able as a general purpose input and or HALT restart input
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values
TL DD12864 – 9
TL DD12864 – 8
FIGURE 7 Crystal and R C Oscillator Diagrams
TABLE I Crystal Oscillator Configuration T_A e 25 C
R1 R2 C1
(kX) (MX) (pF)
C2
(pF)
CKI Freq
(MHz)
Conditions
0
1 30 30 – 36
10
V_CC e 5V
0
1 30 30 – 36
4
V_CC e 5V
0
1 200 100 – 150 0 455 V_CC e 5V
TABLE II RC Oscillator Configuration T_A e 25 C
R
(kX)
C
(pF)
CKI Freq
(MHz)
Instr Cycle
(ms)
Conditions
3 3 82 2 2 to 2 7 3 7 to 4 6
5 6 100 1 1 to 1 3 7 4 to 9 0
6 8 100 0 9 to 1 1 8 8 to 10 8
V_CC e 5V
V_CC e 5V
V_CC e 5V
Note 3k s R s 200k
50 pF s C s 200 pF
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