COP87L88KG Datasheet, PDF (24/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with UART and Three Multi-Function Timers

Comparators (Continued)
CMPSL REGISTER (ADDRESS X’00B7)
The CMPSL register contains the following bits
CMP1EN Enable comparator 1
CMP1RD
Comparator 1 result (this is a read only bit
which will read as 0 if the comparator is not
enabled)
CMP10E Selects pin I3 as comparator 1 output provided
that CMPIEN is set to enable the comparator
CMP2EN Enable comparator 2
CMP2RD
Comparator 2 result (this is a read only bit
which will read as 0 if the comparator is not
enabled)
CMP20E Selects pin I6 as comparator 2 output provided
that CMP2EN is set to enable the comparator
Unused CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Unused
Bit 7
Bit 0
Note that the two unused bits of CMPSL may be used as
software flags
Comparator outputs have the same spec as Ports L and G
except that the rise and fall times are symmetrical
Interrupts
The device supports a vectored interrupt scheme It sup-
ports a total of fourteen interrupt sources The following ta-
ble lists all the possible interrupt sources their arbitration
ranking and the memory locations reserved for the interrupt
vector for each source
Two bytes of program memory space are reserved for each
interrupt source All interrupt sources except the software
interrupt are maskable Each of the maskable interrupts
have an Enable bit and one or more Pending bit A maska-
ble interrupt is active if its associated enable and pending
bits are set If GIE e 1 and an interrupt is active then the
processor will be interrupted as soon as it is ready to start
executing an instruction except if the above conditions hap-
pen during the Software Trap service routine This excep-
tion is described in the Software Trap sub-section
The interruption process is accomplished with the INTR in-
struction (opcode 00) which is jammed inside the Instruc-
tion Register and replaces the opcode about to be execut-
ed The following steps are performed for every interrupt
1 The GIE (Global Interrupt Enable) bit is reset
2 The address of the instruction about to be executed is
pushed into the stack
3 The PC (Program Counter) branches to address 00FF
This procedure takes 7 t_c cycles to execute
Arbitration
Ranking
Source
Description
Vector
Address
Hi-Low Byte
(1) Highest
Software
INTR Instruction
0yFE – 0yFF
(2)
Reserved
0yFC – 0yFD
(3)
External
G0
0yFA – 0yFB
(4)
Timer T0
Underflow
0yF8 – 0yF9
(5)
Timer T1
T1A Underflow
0yF6 – 0yF7
(6)
Timer T1
T1B
0yF4 – 0yF5
(7)
MICROWIRE PLUS
BUSY Low
0yF2 – 0yF3
(8)
Reserved
0yF0 – 0yF1
(9)
UART
Receive
0yEE – 0yEF
(10)
UART
Transmit
0yEC – 0yED
(11)
Timer T2
T2A Underflow
0yEA – 0yEB
(12)
Timer T2
T2B
0yE8 – 0yE9
(13)
Timer T3
T3A Underflow
0yE6 – 0yE7
(14)
Timer T3
T3B
0yE4 – 0yE5
(15)
Port L Wakeup
Port L Edge
0yE2 – 0yE3
(16) Lowest
Default VIS
Reserved
0yE0 – 0yE1
y is a variable which represents the VIS block VIS and the vector table must be located in the same 256-byte
block except if VIS is located at the last address of a block In this case the table must be in the next block
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