COP87L88KG Datasheet, PDF (23/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with UART and Three Multi-Function Timers

Baud Clock Generation (Continued)
Where
BR is the Baud Rate
Fc is the CKI frequency
N is the Baud Rate Divisor (Table IV)
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table III)
Note In the Synchronous Mode the divisor 16 is replaced by two
Example
Asynchronous Mode
Crystal Frequency e 5 MHz
Desired baud rate e 9600
Using the above equation N c P can be calculated first
N c P e (5 c 106) (16 c 9600) e 32 552
Now 32 552 is divided by each Prescaler Factor (Table III)
to obtain a value closest to an integer This factor happens
to be 6 5 (P e 6 5)
N e 32 552 6 5 e 5 008 (N e 5)
The programmed value (from Table III) should be 4 (N b 1)
Using the above values calculated for N and P
BR e (5 c 106) (16 c 5 c 6 5) e 9615 384
% error e (9615 385 b 9600) 9600 e 0 16
Effect of HALT IDLE
The UART logic is reinitialized when either the HALT or
IDLE modes are entered This reinitialization sets the TBMT
flag and resets all read only bits in the UART control and
status registers Read Write bits remain unchanged The
Transmit Buffer (TBUF) is not affected but the Transmit
Shift register (TSFT) bits are set to one The receiver regis-
ters RBUF and RSFT are not affected
The device will exit from the HALT IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device
Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RDX pin This
selection is done by setting bit 3 of WKEN (Wakeup Enable)
register The Wakeup trigger condition is then selected to
be high to low transition This is done via the WKEDG regis-
ter (Bit 3 is one )
If the device is halted and crystal oscillator is used the
Wakeup signal will not start the chip running immediately
because of the finite start up time requirement of the crystal
oscillator The idle timer (T0) generates a fixed (256 t_c) de-
lay to ensure that the oscillator has indeed stabilized before
allowing the device to execute code The user has to con-
sider this delay when data transfer is expected immediately
after exiting the HALT mode
Diagnostic
Bits CHARL0 and CHARL1 in the ENU register provide a
loopback feature for diagnostic testing of the UART When
these bits are set to one the following occur The receiver
input pin (RDX) is internally connected to the transmitter
output pin (TDX) the output of the Transmitter Shift Regis-
ter is ‘‘looped back’’ into the Receive Shift Register input In
this mode data that is transmitted is immediately received
This feature allows the processor to verify the transmit and
receive data paths of the UART
Note that the framing format for this mode is the nine bit
format one Start bit nine data bits and 7 8 one or two
Stop bits Parity is not generated or verified in this mode
Attention Mode
The UART Receiver section supports an alternate mode of
operation referred to as ATTENTION Mode This mode of
operation is selected by the ATTN bit in the ENUR register
The data format for transmission must also be selected as
having nine Data bits and either 7 8 one or two Stop bits
The ATTENTION mode of operation is intended for use in
networking the device with other processors Typically in
such environments the messages consists of device ad-
dresses indicating which of several destinations should re-
ceive them and the actual data This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1 If the ninth bit is reset to a
zero the byte is a Data byte
While in ATTENTION mode the UART monitors the com-
munication flow but ignores all characters until an address
character is received Upon receiving an address character
the UART signals that the character is ready by setting the
RBFL flag which in turn interrupts the processor if UART
Receiver interrupts are enabled The ATTN bit is also
cleared automatically at this point so that data characters
as well as address characters are recognized Software ex-
amines the contents of the RBUF and responds by deciding
either to accept the subsequent data stream (by leaving the
ATTN bit reset) or to wait until the next address character is
seen (by setting the ATTN bit again)
Operation of the UART Transmitter is not affected by selec-
tion of this Mode The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately The value of
the ninth bit received is obtained by reading RBIT9 Since
this bit is located in ENUR register where the error flags
reside a bit operation on it will reset the error flags
Comparators
The device contains two differential comparators each with
a pair of inputs (positive and negative) and an output Ports
I1 – I3 and I4 – I6 are used for the comparators The following
is the Port I assignment
I1 Comparator1 negative input
I2 Comparator1 positive input
I3 Comparator1 output
I4 Comparator2 negative input
I5 Comparator2 positive input
I6 Comparator2 output
A Comparator Select Register (CMPSL) is used to enable
the comparators read the outputs of the comparators inter-
nally and enable the outputs of the comparators to the pins
Two control bits (enable and output enable) and one result
bit are associated with each comparator The comparator
result bits (CMP1RD and CMP2RD) are read only bits which
will read as zero if the associated comparator is not en-
abled The Comparator Select Register is cleared with
reset resulting in the comparators being disabled The com-
parators should also be disabled before entering either the
HALT or IDLE modes in order to save power The configura-
tion of the CMPSL register is as follows
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