DS99R103_0710 Datasheet, PDF (4/24 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Symbol
Parameter
I_DDR
Deserializer (Rx)
Total Supply Current
(includes load current)
Deserializer (Rx)
Total Supply Current
(includes load current)
I_DDRZ
Deserializer (Rx)
Supply Current Power-down
Conditions
C_L = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)
C_L = 8 pF LVCMOS Output
Random pattern
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
R_IN+/ R_IN- = 0V)
Pin/Freq.
f = 40 MHz
f = 40 MHz
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
(Figure 5)
(Figure 4)
(Note 9)
Min Typ Max Units
95 mA
90 mA
1 50 µA
Min Typ Max Units
25 T 333 ns
0.4T 0.5T 0.6T ns
0.4T 0.5T 0.6T ns
3 6 ns
33
ps
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_LLHT
t_LHLT
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
R_L = 100Ω, (Figure 3)
C_L = 10 pF to GND
VODSEL = L
t_DIS
DIN (23:0) Setup to TCLK
R_L = 100Ω,
5
t_DIH
DIN (23:0) Hold from TCLK
C_L = 10 pF to GND
5
(Note 8)
t_HZD
DOUT ± HIGH to TRI-STATE Delay
R_L = 100Ω,
t_LZD
DOUT ± LOW to TRI-STATE Delay
C_L = 10 pF to GND
t_ZHD
DOUT ± TRI-STATE to HIGH Delay
(Figure 6) (Note 5)
t_ZLD
DOUT ± TRI-STATE to LOW Delay
t_PLD
Serializer PLL Lock Time
R_L = 100Ω, (Figure 7)
t_SD
Serializer Delay
R_L = 100Ω, (Figure 8)
VODSEL = L, TRFB = H
R_L = 100Ω, (Figure 8)
VODSEL = L, TRFB = L
TxOUT_E_O
TxOUT_Eye_Opening
(respect to ideal)
3–40 MHz
(Figure 9) (Notes 9, 13)
Typ
10
3.5T + 2.85
3.5T + 2.85
0.68
Max Units
0.6
ns
0.6
ns
ns
ns
15
ns
15
ns
200
ns
200
ns
ms
3.5T
+ 10
ns
3.5T
+ 10
ns
UI
(Note 10)
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP
Receiver out Clock Period
t_RCP = t_TCP
RCLK
(Note 8)
25
T
t_RDC
RCLK Duty Cycle
RCLK
45
50
t_CLH
LVCMOS Low-to-High
C_L = 8 pF
ROUT [23:0],
2.5
Transition Time
(lumped load)
LOCK, RCLK
t_CHL
LVCMOS High-to-Low
(Figure 11)
Transition Time
2.5
Max Units
333
ns
55
%
3.5
ns
3.5
ns
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