DS99R103_0710 Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R104 Deserializer Pin Descriptions
Pin # Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
13-16, ROUT[15:8] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
21-24
3-6, ROUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
9-12
18 RCLK
LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43 RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48 REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB LVCMOS_I Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
17 LOCK
LVCMOS_O
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
2
RESRVD
LVCMOS_I RESERVED – This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
41 RIN+
LVDS_I
Receiver LVDS True (+) Input This input is intended to be terminated with a 100 ohm load to
the RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
42 RIN−
LVDS_I
Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100 ohm load
to the RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
39 VDDIR
VDD
Analog LVDS Voltage supply, Power
40 VSSIR
GND
Analog LVDS Ground
47 VDDPR0
VDD
Analog Voltage supply, PLL Power
46 VSSPR0
GND
Analog Ground, PLL Ground
45 VDDPR1
VDD
Analog Voltage supply, PLL VCO Power
44 VSSPR1
GND
Analog Ground, PLL VCO Ground
37 VDDR1
VDD
Digital Voltage supply, Logic Power
38 VSSR1
GND
Digital Ground, Logic Ground
36 VDDR0
VDD
Digital Voltage supply, Logic Power
35 VSSR0
GND
Digital Ground, Logic Ground
30
VDDOR1
VDD
Digital Voltage supply, LVCMOS Output Power
29 VSSOR1
GND
Digital Ground, LVCMOS Output Ground
20
VDDOR2
VDD
Digital Voltage supply, LVCMOS Output Power
19 VSSOR2
GND
Digital Ground, LVCMOS Output Ground
7
VDDOR3
VDD
Digital Voltage supply, LVCMOS Output Power
8
VSSOR3
GND
Digital Ground, LVCMOS Output Ground
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