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DS99R103_0710 Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Symbol
Parameter
Conditions
Pin/Freq.
LVDS DC SPECIFICATIONS
VTH
Differential Threshold High VCM = +1.2V
Voltage
Rx: RIN+, RIN−
VTL
Differential Threshold Low
Voltage
IIN
Input Current
VIN = +2.4V,
VDD = 3.6V
VIN = 0V, VDD = 3.6V
RT
Differential Internal
Termination Resistance
VOD
Output Differential Voltage RL = 100Ω, w/o Pre-emphasis
Tx: DOUT+, DOUT−
(DOUT+)–(DOUT−)
VODSEL = L (Figure 10)
RL = 100Ω, w/o Pre-emphasis
VODSEL = H (Figure 10)
ΔVOD
Output Differential Voltage
Unbalance
RL = 100Ω, w/o Pre-emphasis
VOS
ΔVOS
IOS
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
RL = 100Ω, w/o Pre-emphasis
RL = 100Ω, w/o Pre-emphasis
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
IOZ
TRI-STATE Output Current TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs
IDDT
Serializer (Tx)
Total Supply Current
(includes load current)
RL = 100Ω
Pre-emphasis = OFF
VODSEL = L
Checker-board pattern (Figure 1)
f = 40 MHz
RL = 100Ω
RPRE = 6 kΩ
VODSEL = L
Checker-board pattern (Figure 1)
f = 40 MHz
Serializer (Tx)
Total Supply Current
(includes load current)
RL = 100Ω
Pre-emphasis = OFF
VODSEL = H
Checker-board pattern (Figure 1)
f = 40 MHz
RL = 100Ω
RPRE = 6 kΩ
VODSEL = H
Checker-board pattern (Figure 1)
f = 40 MHz
IDDTZ
Serializer (Tx)
TPWDNB = 0V
Supply Current Power-down (All other LVCMOS Inputs = 0V)
Min Typ Max Units
+50 mV
−50
mV
±300 µA
±300 µA
90 100 130 Ω
250 400 600 mV
450 750 1200 mV
4 50 mV
1.00 1.25 1.50 V
1 50 mV
−2 −5 −8 mA
−7 −10 −13 mA
−15 ±1 +15 µA
40 80 mA
45 85 mA
40 85 mA
45 90 mA
14 250 µA
3
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