DS92LV16 Datasheet, PDF (4/19 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

Serializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
DO ± HIGH to
t_HZD
TRI-STATE Delay
2.3
DO ± LOW to
t_LZD
TRI-STATE Delay
Figure 7 (Note 4)
1.9
t_ZHD
DO ± TRI-STATE to
HIGH Delay
R_L = 100Ω,
C_L=10pF to GND
1.0
DO ± TRI-STATE to
t_ZLD
LOW Delay
1.0
t_SPW
t_PLD
t_SD
t_RJIT
t_DJIT
SYNC Pulse Width
Serializer PLL Lock Time
Serializer Delay
Random Jitter
Deterministic Jitter
Figure 15
Figure 8
R_L = 100Ω
Figure 9 R_L = 100Ω
35 MHz
80 MHz
5*t_TCP
510*t_TCP
t_TCP + 1.0
-240
-75
t_TCP + 2.0
10
Max
10
10
10
10
6*t_TCP
513*t_TCP
t_TCP + 4.0
140
100
Units
ns
ns
ns
ns
ns
ns
ns
ps(rms)
ps
ps
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
t_RFCP
t_RFDC
t_RFCP /
t_TCP
t_RFTT
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK
REFCLK Transition Time
12.5
T
40
40
50
60
0.95
1.05
6
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP
t_RDC
t_CLH
t_CHL
t_ROS
t_ROH
Receiver out Clock
Period
RCLK Duty Cycle
CMOS/TTL
Low-to-High
Transition Time
CMOS/TTL
High-to-Low
Transition Time
ROUT (0-9) Setup
Data to RCLK
ROUT (0-9) Hold
Data to RCLK
Figure 9
t_RCP = t_TCP
CL = 15 pF
Figure 4
Figure 11
RCLK
12.5
RCLK
45
50
2
Rout(0-9),
LOCK,
RCLK
0.35*t_RCP
−0.35*t_RCP
2
0.5*t_RCP
−0.5*t_RCP
HIGH to TRI-STATE
t_HZR
Delay
2.2
LOW to TRI-STATE
t_LZR
Delay
2.2
Rout(0-9),
Figure 12
TRI-STATE to HIGH
LOCK
t_ZHR
Delay
2.3
TRI-STATE to LOW
t_ZLR
Delay
2.9
t_DD Deserializer Delay
RCLK
1.75*t_RCP
+2
1.75*t_RCP + 5
Max
40
55
4
4
10
10
10
10
1.75*t_RCP + 7
Units
ns
%
ns
Units
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
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