DS92LV16 Datasheet, PDF (18/19 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

Pin Descriptions
Pin #
1
2
3
4
5, 10, 11, 15
6,9,12,16
7
8
13
14
17
18
19
20
Pin Name
RPWDN*
REN
CONFIG1
REFCLK
AVDD
AGND
RIN+
RIN-
DO+
DO-
TCLK
CONFIG2
DEN
SYNC
21, 22, 23, 24, 25, 26,
27, 28, 33, 34, 35, 36,
37, 38, 39, 40
29,32
30,31
41, 44, 51, 52, 59, 60,
61, 68, 80
42
43, 50, 53, 58, 62, 69
45, 46, 47, 48, 54, 55,
56, 57, 64, 65, 66, 67,
70, 71, 72, 73
49
DIN (0:15)
PGND
PVDD
DGND
TPWDN*
DVDD
ROUT (0:15)
RCLK
63
74,76
75,77
78
LOCK*
PGND
PVDD
LINE_LE
79
LOCAL_LE
I/O
CMOS, I
CMOS, I
CMOS, I
LVDS, I
LVDS, I
LVDS, O
LVDS, O
CMOS, I
CMOS, I
CMOS, I
CMOS, I
Description
RPWDN* = Low will put the Receiver in low power, stand-by,
mode. Note: The Receiver PLL will lose lock.(Note 8)
REN = Low will disable the Receiver outputs. Receiver PLL
remains locked. (See LOCK pin description)(Note 8)
Configuration pin - strap or tie this pin to High with pull-up resistor.
No-connect or Low reserved for future use.
Frequency reference clock input for the receiver.
Analog Voltage Supply
Analog Ground
Receiver LVDS True Input
Receiver LVDS Inverting Input
Transmitter LVDS True Output
Transmitter LVDS Inverting Output
Transmitter reference clock. Used to strobe data at the DIN Inputs
and to drive the transmitter PLL. See TCLK Timing Requirements.
Configuration pin - strap or tie this pin to High with pull-up resistor.
No-connect or Low reserved for future use.
DEN = Low will disable the Transmitter outputs. The transmitter
PLL will remain locked.(Note 8)
SYNC = High will cause the transmitter to ignore the data inputs
and send SYNC patterns to provide a locking reference to
receiver(s). See Functional Description.(Note 8)
Transmitter data inputs.(Note 8)
PLL Ground.
PLL Voltage supply.
Digital Ground.
CMOS, I TPWDN* = Low will put the Transmitter in low power, stand-by
mode. Note: The transmitter PLL will lose lock.(Note 8)
Digital Voltage Supplies.
CMOS, O Receiver Outputs.
CMOS, O Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT (0:15). LVCMOS Level
output.
CMOS, O LOCK* indicates the status of the receiver PLL. LOCK = H -
receiver PLL is unlocked, LOCK = L - receiver PLL is locked.
PLL Grounds.
PLL Voltage Supplies.
CMOS, I LINE_LE = High enables the receiver loopback mode. Data
received at the RIN+/- inputs is fed back through the DO+/-
outputs.(Note 8)
CMOS, I LOCAL_LE = High enables the transmitter loopback mode. Date
received at the DIN inputs is fed back through the ROUT
outputs.(Note 8)
Note 8: Input defaults to ’low’ state when left open due to internal pull-device.
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